Searched hist:"7953354 b07bba8fa9599bf5d212308e6cdf9cbe2" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/arch/mips/include/asm/ |
| H A D | cm.h | diff 7953354b07bba8fa9599bf5d212308e6cdf9cbe2 Wed Sep 21 05:18:55 CDT 2016 Paul Burton <paul.burton@imgtec.com> MIPS: Join the coherent domain when a CM is present
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| /openbmc/u-boot/arch/mips/lib/ |
| H A D | cache_init.S | diff 7953354b07bba8fa9599bf5d212308e6cdf9cbe2 Wed Sep 21 05:18:55 CDT 2016 Paul Burton <paul.burton@imgtec.com> MIPS: Join the coherent domain when a CM is present
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|