Searched hist:"6 efd55995a224787baa712500b82ef21a148d38e" (Results 1 – 5 of 5) sorted by relevance
| /openbmc/qemu/linux-user/microblaze/ |
| H A D | cpu_loop.c | diff 6efd55995a224787baa712500b82ef21a148d38e Thu Aug 20 00:37:40 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of ESR
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| /openbmc/qemu/target/microblaze/ |
| H A D | op_helper.c | diff 6efd55995a224787baa712500b82ef21a148d38e Thu Aug 20 00:37:40 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of ESR
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | helper.c | diff 6efd55995a224787baa712500b82ef21a148d38e Thu Aug 20 00:37:40 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of ESR
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | cpu.h | diff 6efd55995a224787baa712500b82ef21a148d38e Thu Aug 20 00:37:40 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of ESR
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | translate.c | diff 6efd55995a224787baa712500b82ef21a148d38e Thu Aug 20 00:37:40 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of ESR
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|