Searched hist:"681 ae1adc42387dae71bc6aa8126215bddc55607" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe_ptp.c | diff 681ae1adc42387dae71bc6aa8126215bddc55607 Tue May 01 00:24:41 CDT 2012 Jacob E Keller <jacob.e.keller@intel.com> ixgbe: Enable timesync clock-out feature for PPS support on X540
This patch enables the PPS system in the PHC framework, by enabling
the clock-out feature on the X540 device. Causes the SDP0 to be set as
a 1Hz clock. Also configures the timesync interrupt cause in order to
report each pulse to the PPS via the PHC framework, which can be used
for general system clock synchronization. (This allows a stable method
for tuning the general system time via the on-board SYSTIM register
based clock.)
Signed-off-by: Jacob E Keller <jacob.e.keller@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
|
| H A D | ixgbe_type.h | diff 681ae1adc42387dae71bc6aa8126215bddc55607 Tue May 01 00:24:41 CDT 2012 Jacob E Keller <jacob.e.keller@intel.com> ixgbe: Enable timesync clock-out feature for PPS support on X540
This patch enables the PPS system in the PHC framework, by enabling
the clock-out feature on the X540 device. Causes the SDP0 to be set as
a 1Hz clock. Also configures the timesync interrupt cause in order to
report each pulse to the PPS via the PHC framework, which can be used
for general system clock synchronization. (This allows a stable method
for tuning the general system time via the on-board SYSTIM register
based clock.)
Signed-off-by: Jacob E Keller <jacob.e.keller@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
|
| H A D | ixgbe.h | diff 681ae1adc42387dae71bc6aa8126215bddc55607 Tue May 01 00:24:41 CDT 2012 Jacob E Keller <jacob.e.keller@intel.com> ixgbe: Enable timesync clock-out feature for PPS support on X540
This patch enables the PPS system in the PHC framework, by enabling
the clock-out feature on the X540 device. Causes the SDP0 to be set as
a 1Hz clock. Also configures the timesync interrupt cause in order to
report each pulse to the PPS via the PHC framework, which can be used
for general system clock synchronization. (This allows a stable method
for tuning the general system time via the on-board SYSTIM register
based clock.)
Signed-off-by: Jacob E Keller <jacob.e.keller@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
|
| H A D | ixgbe_main.c | diff 681ae1adc42387dae71bc6aa8126215bddc55607 Tue May 01 00:24:41 CDT 2012 Jacob E Keller <jacob.e.keller@intel.com> ixgbe: Enable timesync clock-out feature for PPS support on X540
This patch enables the PPS system in the PHC framework, by enabling
the clock-out feature on the X540 device. Causes the SDP0 to be set as
a 1Hz clock. Also configures the timesync interrupt cause in order to
report each pulse to the PPS via the PHC framework, which can be used
for general system clock synchronization. (This allows a stable method
for tuning the general system time via the on-board SYSTIM register
based clock.)
Signed-off-by: Jacob E Keller <jacob.e.keller@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
|