Searched hist:"6673 c2763f6f999fc32cff1833c7d4d6d35f787b" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/mips/include/uapi/asm/ |
| H A D | inst.h | diff 6673c2763f6f999fc32cff1833c7d4d6d35f787b Sun Jun 04 07:26:52 CDT 2023 Siarhei Volkau <lis8215@gmail.com> MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccess
The LXW, LXH, LXHU opcodes are part of the MXU ASE found in Ingenic
XBurst based SoCs.
While technically part of the MXU ASE, they do not touch any of the SIMD
registers, and can be used even when the MXU ASE is disabled.
This patch makes it possible to emulate unaligned access for those
instructions.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| /openbmc/linux/arch/mips/kernel/ |
| H A D | unaligned.c | diff 6673c2763f6f999fc32cff1833c7d4d6d35f787b Sun Jun 04 07:26:52 CDT 2023 Siarhei Volkau <lis8215@gmail.com> MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccess
The LXW, LXH, LXHU opcodes are part of the MXU ASE found in Ingenic
XBurst based SoCs.
While technically part of the MXU ASE, they do not touch any of the SIMD
registers, and can be used even when the MXU ASE is disabled.
This patch makes it possible to emulate unaligned access for those
instructions.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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