Searched hist:"654 c293e1687b31819f9bf1ac71b5a85a8053210" (Results 1 – 5 of 5) sorted by relevance
| /openbmc/linux/drivers/mfd/ |
| H A D | rz-mtu3.h | 654c293e1687b31819f9bf1ac71b5a85a8053210 Thu Mar 30 06:16:28 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> mfd: Add Renesas RZ/G2L MTU3a core driver
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoCs. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
The 8/16/32 bit registers are mixed in each channel.
Add MTU3a core driver for RZ/G2L SoC. The core driver shares the
clk and channel register access for the other child devices like
Counter, PWM and Clock event.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330111632.169434-3-biju.das.jz@bp.renesas.com
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| H A D | rz-mtu3.c | 654c293e1687b31819f9bf1ac71b5a85a8053210 Thu Mar 30 06:16:28 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> mfd: Add Renesas RZ/G2L MTU3a core driver
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoCs. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
The 8/16/32 bit registers are mixed in each channel.
Add MTU3a core driver for RZ/G2L SoC. The core driver shares the
clk and channel register access for the other child devices like
Counter, PWM and Clock event.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330111632.169434-3-biju.das.jz@bp.renesas.com
|
| H A D | Makefile | diff 654c293e1687b31819f9bf1ac71b5a85a8053210 Thu Mar 30 06:16:28 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> mfd: Add Renesas RZ/G2L MTU3a core driver
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoCs. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
The 8/16/32 bit registers are mixed in each channel.
Add MTU3a core driver for RZ/G2L SoC. The core driver shares the
clk and channel register access for the other child devices like
Counter, PWM and Clock event.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330111632.169434-3-biju.das.jz@bp.renesas.com
|
| H A D | Kconfig | diff 654c293e1687b31819f9bf1ac71b5a85a8053210 Thu Mar 30 06:16:28 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> mfd: Add Renesas RZ/G2L MTU3a core driver
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoCs. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
The 8/16/32 bit registers are mixed in each channel.
Add MTU3a core driver for RZ/G2L SoC. The core driver shares the
clk and channel register access for the other child devices like
Counter, PWM and Clock event.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330111632.169434-3-biju.das.jz@bp.renesas.com
|
| /openbmc/linux/include/linux/mfd/ |
| H A D | rz-mtu3.h | 654c293e1687b31819f9bf1ac71b5a85a8053210 Thu Mar 30 06:16:28 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> mfd: Add Renesas RZ/G2L MTU3a core driver
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoCs. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
The 8/16/32 bit registers are mixed in each channel.
Add MTU3a core driver for RZ/G2L SoC. The core driver shares the
clk and channel register access for the other child devices like
Counter, PWM and Clock event.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330111632.169434-3-biju.das.jz@bp.renesas.com
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