Searched hist:"63 d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/arch/openrisc/include/asm/ |
| H A D | ptrace.h | diff 63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf Fri Apr 14 02:25:58 CDT 2023 Stafford Horne <shorne@gmail.com> openrisc: Support storing and restoring fpu state
OpenRISC floating point state is not so expensive to save as OpenRISC uses
general purpose registers for floating point instructions. We need to save
only the floating point status and control register, FPCSR.
Add support to maintain the FPCSR unconditionally upon exceptions and
switches. On machines that do not support FPU this will always just
store 0x0 and restore is a no-op. On FPU systems this adds an
additional special purpose register read/write and read/write to memory
(already cached).
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| /openbmc/linux/arch/openrisc/kernel/ |
| H A D | entry.S | diff 63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf Fri Apr 14 02:25:58 CDT 2023 Stafford Horne <shorne@gmail.com> openrisc: Support storing and restoring fpu state
OpenRISC floating point state is not so expensive to save as OpenRISC uses
general purpose registers for floating point instructions. We need to save
only the floating point status and control register, FPCSR.
Add support to maintain the FPCSR unconditionally upon exceptions and
switches. On machines that do not support FPU this will always just
store 0x0 and restore is a no-op. On FPU systems this adds an
additional special purpose register read/write and read/write to memory
(already cached).
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| H A D | traps.c | diff 63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf Fri Apr 14 02:25:58 CDT 2023 Stafford Horne <shorne@gmail.com> openrisc: Support storing and restoring fpu state
OpenRISC floating point state is not so expensive to save as OpenRISC uses
general purpose registers for floating point instructions. We need to save
only the floating point status and control register, FPCSR.
Add support to maintain the FPCSR unconditionally upon exceptions and
switches. On machines that do not support FPU this will always just
store 0x0 and restore is a no-op. On FPU systems this adds an
additional special purpose register read/write and read/write to memory
(already cached).
Signed-off-by: Stafford Horne <shorne@gmail.com>
|