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| H A D | cache_init.S | diff 639200f6a0dcfe67e4c923b6108703e192946388 Wed Sep 21 05:18:59 CDT 2016 Paul Burton <paul.burton@imgtec.com> MIPS: Ensure cache ops complete in mips_cache_reset
Ensure that cache operations complete before returning from
mips_cache_reset by placing a completion barrier (sync instruction)
before the return. Without this there is no guarantee that the cache ops
will complete before any subsequent memory accesses, since they are
indexed cache ops & thus not implicitly ordered with memory accesses.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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