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/openbmc/u-boot/arch/mips/lib/
H A Dcache_init.Sdiff 5ef337a0371e2b2c7905e7e20a38b6bfc80bb708 Fri Sep 07 12:02:05 CDT 2018 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> MIPS: cache: make index base address configurable

The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
/openbmc/u-boot/arch/mips/
H A DKconfigdiff 5ef337a0371e2b2c7905e7e20a38b6bfc80bb708 Fri Sep 07 12:02:05 CDT 2018 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> MIPS: cache: make index base address configurable

The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>