Searched hist:"5 e049fce368dfe07702c3664add9ae7b45df1a9a" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/sound/soc/tegra/ |
| H A D | tegra30_ahub.h | diff 5e049fce368dfe07702c3664add9ae7b45df1a9a Fri Oct 11 16:43:17 CDT 2013 Stephen Warren <swarren@nvidia.com> ASoC: tegra: support new register layouts in Tegra124
Tegra124 introduces some small changes to the layout of some registers.
Modify the affected drivers to program those registers appropriately
based on which SoC they're running on.
Tegra124 also introduced some new modules on the AHUB configlink register
bus. These will require new entries in configlink_clocks[] in the AHUB
driver. However, supporting that change likely relies on switching Tegra
to the common reset framework, so I'll defer that change for now.
Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| H A D | tegra30_i2s.h | diff 5e049fce368dfe07702c3664add9ae7b45df1a9a Fri Oct 11 16:43:17 CDT 2013 Stephen Warren <swarren@nvidia.com> ASoC: tegra: support new register layouts in Tegra124
Tegra124 introduces some small changes to the layout of some registers.
Modify the affected drivers to program those registers appropriately
based on which SoC they're running on.
Tegra124 also introduced some new modules on the AHUB configlink register
bus. These will require new entries in configlink_clocks[] in the AHUB
driver. However, supporting that change likely relies on switching Tegra
to the common reset framework, so I'll defer that change for now.
Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| H A D | tegra30_ahub.c | diff 5e049fce368dfe07702c3664add9ae7b45df1a9a Fri Oct 11 16:43:17 CDT 2013 Stephen Warren <swarren@nvidia.com> ASoC: tegra: support new register layouts in Tegra124
Tegra124 introduces some small changes to the layout of some registers.
Modify the affected drivers to program those registers appropriately
based on which SoC they're running on.
Tegra124 also introduced some new modules on the AHUB configlink register
bus. These will require new entries in configlink_clocks[] in the AHUB
driver. However, supporting that change likely relies on switching Tegra
to the common reset framework, so I'll defer that change for now.
Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| H A D | tegra30_i2s.c | diff 5e049fce368dfe07702c3664add9ae7b45df1a9a Fri Oct 11 16:43:17 CDT 2013 Stephen Warren <swarren@nvidia.com> ASoC: tegra: support new register layouts in Tegra124
Tegra124 introduces some small changes to the layout of some registers.
Modify the affected drivers to program those registers appropriately
based on which SoC they're running on.
Tegra124 also introduced some new modules on the AHUB configlink register
bus. These will require new entries in configlink_clocks[] in the AHUB
driver. However, supporting that change likely relies on switching Tegra
to the common reset framework, so I'll defer that change for now.
Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
|