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H A Dnpcm8xx-tip-fw.incdiff 5cecfc9f075a7f76898c6e4ffe97d4a6eec190e4 Fri Jan 13 01:00:50 CST 2023 Tim Lee <timlee660101@gmail.com> meta-nuvoton: npcm8xx-tip-fw: update to 0.5.3.0.4.2

Changelog:

TIP_FW_L0_0.5.3_L1_0.4.2
==============
- TIP_FW L0 version 0.5.3 and L1 version 0.4.2 L1
- FreeRTOS: in case of assert: print useful info.
- NVIC_BMC_reset: clear NVIC int before reloading BMC.
- in BMC reset and spurious interrupt reset: read the int number from
the active and not the pending.
- NVIC_IntHandlerCommon: bug fix: clear correct number.
- Big fix: enable all traps in hardware_app_init.
- Add task bmc_task to handle BMC reset reload.
- Increase heap_size to 0xA000.
- HOSTPER: set to 1 till KCS bug is fixed.
- Flash: check if FIU1 and FIU 0\CS1 are disabled by OTP bit.
- Flash: bug fix: do not enable FIU1 CS2\3.
- Flash: Allow using a 4MB flash for image.
- Update FreeRTOS to none-MPU version.
- Spurious interrupt handling: in case of spurious interrupt print
correct int number + NVIC state, and then clear it.
- OTP version: use two bits for each version number.
- Copy DBGRST too to INTCR2.
- Debug log: bug fix: data corruption in case of a 16MB flash. Replace
the code so that Debug log is 64KB (one flash block). its location is
- split flash for active recovery: 64KB before recovery image.
- two flash mode: last block in active flash.
- UUID: add full data read (wafer, X\Y, year, work week). Note: debug
chips do not contain this info.

TIP FW 0.5.1 L0 0.4.0 L1
==============
- Set RCR regs only in PORST.
- Change RCR values for TIP reset.
- NVIC: print more data on spurious interrupts.
- SPIX - set FIU_FIX to SINGLES. Other FIUs remain in INCREASING mode as
before.

TIP FW 0.5.1 L0 0.4.0 L1 GOOGLE4
==============
- derived from TIP FW 0.5.1 L0 0.4.0 L1

Tested:
buid pass and boot up successful with correct TIP FW latest version.

Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I2b5093470d6caa2e26bb287ec7dda3a8d0c4404c