Searched hist:"5 b0e508415a83989fe704b4718a1a214bc333ca7" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/arch/x86/kernel/ |
| H A D | step.c | diff 5b0e508415a83989fe704b4718a1a214bc333ca7 Mon Mar 10 08:11:17 CDT 2008 Jan Beulich <jbeulich@novell.com> x86: prevent unconditional writes to DebugCtl MSR
Otherwise, enabling (or better, subsequent disabling) of single
stepping would cause a kernel oops on CPUs not having this MSR.
The patch could have been added a conditional to the MSR write in
user_disable_single_step(), but centralizing the updates seems safer
and (looking forward) better manageable.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Markus Metzger <markus.t.metzger@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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| H A D | process_32.c | diff 5b0e508415a83989fe704b4718a1a214bc333ca7 Mon Mar 10 08:11:17 CDT 2008 Jan Beulich <jbeulich@novell.com> x86: prevent unconditional writes to DebugCtl MSR
Otherwise, enabling (or better, subsequent disabling) of single
stepping would cause a kernel oops on CPUs not having this MSR.
The patch could have been added a conditional to the MSR write in
user_disable_single_step(), but centralizing the updates seems safer
and (looking forward) better manageable.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Markus Metzger <markus.t.metzger@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
|
| H A D | process_64.c | diff 5b0e508415a83989fe704b4718a1a214bc333ca7 Mon Mar 10 08:11:17 CDT 2008 Jan Beulich <jbeulich@novell.com> x86: prevent unconditional writes to DebugCtl MSR
Otherwise, enabling (or better, subsequent disabling) of single
stepping would cause a kernel oops on CPUs not having this MSR.
The patch could have been added a conditional to the MSR write in
user_disable_single_step(), but centralizing the updates seems safer
and (looking forward) better manageable.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Markus Metzger <markus.t.metzger@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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