Searched hist:"5 a63426e2a18775ed05b20e3bc90c68bacb1f68a" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/tools/power/x86/turbostat/ |
| H A D | turbostat.c | diff 5a63426e2a18775ed05b20e3bc90c68bacb1f68a Wed Apr 06 16:15:55 CDT 2016 Len Brown <len.brown@intel.com> tools/power turbostat: print IRTL MSRs
Some processors use the Interrupt Response Time Limit (IRTL) MSR value
to describe the maximum IRQ response time latency for deep
package C-states. (Though others have the register, but do not use it)
Lets print it out to give insight into the cases where it is used.
IRTL begain in SNB, with PC3/PC6/PC7, and HSW added PC8/PC9/PC10.
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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| /openbmc/linux/arch/x86/include/asm/ |
| H A D | msr-index.h | diff 5a63426e2a18775ed05b20e3bc90c68bacb1f68a Wed Apr 06 16:15:55 CDT 2016 Len Brown <len.brown@intel.com> tools/power turbostat: print IRTL MSRs
Some processors use the Interrupt Response Time Limit (IRTL) MSR value
to describe the maximum IRQ response time latency for deep
package C-states. (Though others have the register, but do not use it)
Lets print it out to give insight into the cases where it is used.
IRTL begain in SNB, with PC3/PC6/PC7, and HSW added PC8/PC9/PC10.
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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