Searched hist:"5 a53e2c1dc939fea1af92cc126ee546d8211d412" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/hw/intc/ |
| H A D | armv7m_nvic.c | diff 5a53e2c1dc939fea1af92cc126ee546d8211d412 Thu Feb 15 12:29:37 CST 2018 Peter Maydell <peter.maydell@linaro.org> hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
Instead of hardcoding the values of M profile ID registers in the
NVIC, use the fields in the CPU struct. This will allow us to
give different M profile CPU types different ID register values.
This commit includes the addition of the missing ID_ISAR5,
which exists as RES0 in both v7M and v8M.
(The values of the ID registers might be wrong for the M4 --
this commit leaves the behaviour there unchanged.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-2-peter.maydell@linaro.org
|
| /openbmc/qemu/target/arm/ |
| H A D | cpu.c | diff 5a53e2c1dc939fea1af92cc126ee546d8211d412 Thu Feb 15 12:29:37 CST 2018 Peter Maydell <peter.maydell@linaro.org> hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
Instead of hardcoding the values of M profile ID registers in the
NVIC, use the fields in the CPU struct. This will allow us to
give different M profile CPU types different ID register values.
This commit includes the addition of the missing ID_ISAR5,
which exists as RES0 in both v7M and v8M.
(The values of the ID registers might be wrong for the M4 --
this commit leaves the behaviour there unchanged.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-2-peter.maydell@linaro.org
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