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/openbmc/u-boot/drivers/clk/
H A Dclk_zynq.cdiff 58afff43e3a8f31344cbbc6a3f09bd3f7a2a70eb Wed Feb 21 08:06:20 CST 2018 Michal Simek <michal.simek@xilinx.com> clk: zynq: Show watchdog clock rate properly

watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
swdt 4294967290
After:
swdt 111111110

Signed-off-by: Michal Simek <michal.simek@xilinx.com>