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H A Dtranslate.cdiff 54c3e9534f81a733806ac823185918dfe88687a5 Fri Nov 03 12:38:21 CDT 2023 Richard Henderson <richard.henderson@linaro.org> target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL

Align the operation to the 32-byte cacheline.
Use 2 i128 instead of 4 i64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-3-richard.henderson@linaro.org>