Searched hist:"5133 ed17906d1116c7ce47fd49ae77373cd41e29" (Results 1 – 1 of 1) sorted by relevance
| /openbmc/qemu/hw/riscv/ |
| H A D | sifive_u.c | diff 5133ed17906d1116c7ce47fd49ae77373cd41e29 Mon Jun 08 09:17:38 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: sifive_u: Add reset functionality
The HiFive Unleashed board wires GPIO pin#10 to the input of the
system reset signal. Let's set up the GPIO pin#10 and insert a
"gpio-restart" device tree node so that reboot is now functional
with QEMU 'sifive_u' machine.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-10-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|