Searched hist:"4 c6c03be125e9d8477c2d8ef3c3280270956b1fe" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | intel_runtime_pm.c | diff 4c6c03be125e9d8477c2d8ef3c3280270956b1fe Fri Mar 06 12:50:48 CST 2015 Damien Lespiau <damien.lespiau@intel.com> drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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| H A D | i915_irq.c | diff 4c6c03be125e9d8477c2d8ef3c3280270956b1fe Fri Mar 06 12:50:48 CST 2015 Damien Lespiau <damien.lespiau@intel.com> drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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