Searched hist:"4 a0156fbfb78b8006ce9b2ffac9383b7d4a8192b" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/arch/mips/include/asm/ |
| H A D | cpu-features.h | diff 4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b Thu Nov 14 10:12:24 CST 2013 Steven J. Hill <Steven.Hill@imgtec.com> MIPS: features: Add initial support for Segmentation Control registers
MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
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| H A D | cpu.h | diff 4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b Thu Nov 14 10:12:24 CST 2013 Steven J. Hill <Steven.Hill@imgtec.com> MIPS: features: Add initial support for Segmentation Control registers
MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
|
| H A D | mipsregs.h | diff 4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b Thu Nov 14 10:12:24 CST 2013 Steven J. Hill <Steven.Hill@imgtec.com> MIPS: features: Add initial support for Segmentation Control registers
MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
|
| /openbmc/linux/arch/mips/kernel/ |
| H A D | cpu-probe.c | diff 4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b Thu Nov 14 10:12:24 CST 2013 Steven J. Hill <Steven.Hill@imgtec.com> MIPS: features: Add initial support for Segmentation Control registers
MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
|