Searched hist:"446587 a914cfa57c2ce529056a9ca2215bde7111" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/include/hw/misc/ |
| H A D | iotkit-sysinfo.h | diff 446587a914cfa57c2ce529056a9ca2215bde7111 Fri Feb 19 08:45:43 CST 2021 Peter Maydell <peter.maydell@linaro.org> hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
For SSE-300, the SYSINFO register block has two new registers:
* SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3;
since the SSE-300 can only be configured with a single CPU it
is always zero
* IIDR is the subsystem implementation identity register;
its value is set by the SoC integrator, so we plumb this in from
the armsse.c code as we do with SYS_VERSION and SYS_CONFIG
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-11-peter.maydell@linaro.org
|
| /openbmc/qemu/hw/misc/ |
| H A D | iotkit-sysinfo.c | diff 446587a914cfa57c2ce529056a9ca2215bde7111 Fri Feb 19 08:45:43 CST 2021 Peter Maydell <peter.maydell@linaro.org> hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
For SSE-300, the SYSINFO register block has two new registers:
* SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3;
since the SSE-300 can only be configured with a single CPU it
is always zero
* IIDR is the subsystem implementation identity register;
its value is set by the SoC integrator, so we plumb this in from
the armsse.c code as we do with SYS_VERSION and SYS_CONFIG
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-11-peter.maydell@linaro.org
|
| /openbmc/qemu/hw/arm/ |
| H A D | armsse.c | diff 446587a914cfa57c2ce529056a9ca2215bde7111 Fri Feb 19 08:45:43 CST 2021 Peter Maydell <peter.maydell@linaro.org> hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
For SSE-300, the SYSINFO register block has two new registers:
* SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3;
since the SSE-300 can only be configured with a single CPU it
is always zero
* IIDR is the subsystem implementation identity register;
its value is set by the SoC integrator, so we plumb this in from
the armsse.c code as we do with SYS_VERSION and SYS_CONFIG
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-11-peter.maydell@linaro.org
|