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| /openbmc/qemu/target/microblaze/ |
| H A D | op_helper.c | diff 3e0e16ae1e0048a21a91674061ec9c43c5d7a76c Thu Aug 20 00:33:37 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of MSR
The machine status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| H A D | helper.c | diff 3e0e16ae1e0048a21a91674061ec9c43c5d7a76c Thu Aug 20 00:33:37 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of MSR
The machine status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| H A D | cpu.h | diff 3e0e16ae1e0048a21a91674061ec9c43c5d7a76c Thu Aug 20 00:33:37 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of MSR
The machine status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| H A D | translate.c | diff 3e0e16ae1e0048a21a91674061ec9c43c5d7a76c Thu Aug 20 00:33:37 CDT 2020 Richard Henderson <richard.henderson@linaro.org> target/microblaze: Fix width of MSR
The machine status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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