Searched hist:"3 b756ccddb8a75563900cd603c83160b43f3d691" (Results 1 – 5 of 5) sorted by relevance
| /openbmc/linux/arch/csky/mm/ |
| H A D | tlb.c | diff 3b756ccddb8a75563900cd603c83160b43f3d691 Wed Dec 23 23:59:57 CST 2020 Guo Ren <guoren@linux.alibaba.com> csky: Fix TLB maintenance synchronization problem
TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.
CPU0 CPU1
=============== ===============
set_pte
sync_is() -> See the previous set_pte for all harts
tlbi.vas -> Invalidate all harts TLB entry & flush pipeline
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
|
| H A D | init.c | diff 3b756ccddb8a75563900cd603c83160b43f3d691 Wed Dec 23 23:59:57 CST 2020 Guo Ren <guoren@linux.alibaba.com> csky: Fix TLB maintenance synchronization problem
TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.
CPU0 CPU1
=============== ===============
set_pte
sync_is() -> See the previous set_pte for all harts
tlbi.vas -> Invalidate all harts TLB entry & flush pipeline
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
|
| /openbmc/linux/arch/csky/abiv1/inc/abi/ |
| H A D | ckmmu.h | diff 3b756ccddb8a75563900cd603c83160b43f3d691 Wed Dec 23 23:59:57 CST 2020 Guo Ren <guoren@linux.alibaba.com> csky: Fix TLB maintenance synchronization problem
TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.
CPU0 CPU1
=============== ===============
set_pte
sync_is() -> See the previous set_pte for all harts
tlbi.vas -> Invalidate all harts TLB entry & flush pipeline
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
|
| /openbmc/linux/arch/csky/abiv2/inc/abi/ |
| H A D | ckmmu.h | diff 3b756ccddb8a75563900cd603c83160b43f3d691 Wed Dec 23 23:59:57 CST 2020 Guo Ren <guoren@linux.alibaba.com> csky: Fix TLB maintenance synchronization problem
TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.
CPU0 CPU1
=============== ===============
set_pte
sync_is() -> See the previous set_pte for all harts
tlbi.vas -> Invalidate all harts TLB entry & flush pipeline
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
|
| /openbmc/linux/arch/csky/include/asm/ |
| H A D | mmu_context.h | diff 3b756ccddb8a75563900cd603c83160b43f3d691 Wed Dec 23 23:59:57 CST 2020 Guo Ren <guoren@linux.alibaba.com> csky: Fix TLB maintenance synchronization problem
TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.
CPU0 CPU1
=============== ===============
set_pte
sync_is() -> See the previous set_pte for all harts
tlbi.vas -> Invalidate all harts TLB entry & flush pipeline
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
|