Searched hist:"35780 e860f7d4a5f33f6ceadf09038ee26f1ef43" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/i2c/ |
| H A D | i2c-davinci.txt | diff 35780e860f7d4a5f33f6ceadf09038ee26f1ef43 Mon Sep 14 04:03:50 CDT 2015 Alexander Sverdlin <alexander.sverdlin@nokia.com> i2c: davinci: Optimize clock generation on Keystone SoC
According to "KeyStone Architecture Inter-IC Control Bus User Guide", fixed
additive part of frequency divisors (referred as "d" in the code and datasheet)
always equals to 6, independent of module clock prescaler.
module clock frequency
master clock frequency = ----------------------
(ICCL + 6) + (ICCH + 6)
It was not the case with original Davinci IP. Introduce new compatible property
"ti,keystone-i2c", which triggers special handling in the driver.
Without this change Keystone-based systems (having 204.8MHz input clock) choose
prescaler 29 (PSC=28). Using d=5 in this case leads to bus bitrate ~353kHz
instead of requested 400kHz. After correction, assuming d=6 bus rate is ~392kHz.
This gives ~11% transfer rate increase.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Hemanth Guruva Reddy <hemanth.guruva_reddy@nokia.com>
Tested-by: Lukasz Gemborowski <lukasz.gemborowski@nokia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
|
| /openbmc/linux/drivers/i2c/busses/ |
| H A D | i2c-davinci.c | diff 35780e860f7d4a5f33f6ceadf09038ee26f1ef43 Mon Sep 14 04:03:50 CDT 2015 Alexander Sverdlin <alexander.sverdlin@nokia.com> i2c: davinci: Optimize clock generation on Keystone SoC
According to "KeyStone Architecture Inter-IC Control Bus User Guide", fixed
additive part of frequency divisors (referred as "d" in the code and datasheet)
always equals to 6, independent of module clock prescaler.
module clock frequency
master clock frequency = ----------------------
(ICCL + 6) + (ICCH + 6)
It was not the case with original Davinci IP. Introduce new compatible property
"ti,keystone-i2c", which triggers special handling in the driver.
Without this change Keystone-based systems (having 204.8MHz input clock) choose
prescaler 29 (PSC=28). Using d=5 in this case leads to bus bitrate ~353kHz
instead of requested 400kHz. After correction, assuming d=6 bus rate is ~392kHz.
This gives ~11% transfer rate increase.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Hemanth Guruva Reddy <hemanth.guruva_reddy@nokia.com>
Tested-by: Lukasz Gemborowski <lukasz.gemborowski@nokia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
|