Searched hist:"33 b5c9b2092e10fa3b8b325823c846368f25bba9" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/arch/mips/lib/ |
| H A D | cache_init.S | diff 33b5c9b2092e10fa3b8b325823c846368f25bba9 Wed Sep 21 05:18:49 CDT 2016 Paul Burton <paul.burton@imgtec.com> MIPS: Enable use of the instruction cache earlier
Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| /openbmc/u-boot/arch/mips/cpu/ |
| H A D | start.S | diff 33b5c9b2092e10fa3b8b325823c846368f25bba9 Wed Sep 21 05:18:49 CDT 2016 Paul Burton <paul.burton@imgtec.com> MIPS: Enable use of the instruction cache earlier
Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|