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| /openbmc/qemu/target/sparc/ |
| H A D | cpu-feature.h.inc | diff 3335a04806d337c69f44a707cdc27515d6c91d84 Sat Nov 04 14:21:37 CDT 2023 Richard Henderson <richard.henderson@linaro.org> target/sparc: Add feature bits for VIS 3
The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus. For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| H A D | translate.c | diff 3335a04806d337c69f44a707cdc27515d6c91d84 Sat Nov 04 14:21:37 CDT 2023 Richard Henderson <richard.henderson@linaro.org> target/sparc: Add feature bits for VIS 3
The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus. For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|