Searched hist:"318 df7238b9f842af96aad01ec183012c8fecab9" (Results 1 – 6 of 6) sorted by relevance
| /openbmc/qemu/disas/ |
| H A D | riscv-xthead.h | 318df7238b9f842af96aad01ec183012c8fecab9 Mon Jun 12 06:10:34 CDT 2023 Christoph Müllner <christoph.muellner@vrull.eu> disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| H A D | riscv-xthead.c | 318df7238b9f842af96aad01ec183012c8fecab9 Mon Jun 12 06:10:34 CDT 2023 Christoph Müllner <christoph.muellner@vrull.eu> disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | riscv.h | diff 318df7238b9f842af96aad01ec183012c8fecab9 Mon Jun 12 06:10:34 CDT 2023 Christoph Müllner <christoph.muellner@vrull.eu> disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | meson.build | diff 318df7238b9f842af96aad01ec183012c8fecab9 Mon Jun 12 06:10:34 CDT 2023 Christoph Müllner <christoph.muellner@vrull.eu> disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | riscv.c | diff 318df7238b9f842af96aad01ec183012c8fecab9 Mon Jun 12 06:10:34 CDT 2023 Christoph Müllner <christoph.muellner@vrull.eu> disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| /openbmc/qemu/target/riscv/ |
| H A D | cpu_cfg.h | diff 318df7238b9f842af96aad01ec183012c8fecab9 Mon Jun 12 06:10:34 CDT 2023 Christoph Müllner <christoph.muellner@vrull.eu> disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|