Searched hist:"314 d3eff66f41f39191aaca2e5f6e3dc81480c1b" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/target/i386/tcg/ |
| H A D | fpu_helper.c | diff 314d3eff66f41f39191aaca2e5f6e3dc81480c1b Wed Oct 19 07:01:36 CDT 2022 Paolo Bonzini <pbonzini@redhat.com> target/i386: introduce function to set rounding mode from FPCW or MXCSR bits
VROUND, FSTCW and STMXCSR all have to perform the same conversion from
x86 rounding modes to softfloat constants. Since the ISA is consistent
on the meaning of the two-bit rounding modes, extract the common code
into a wrapper for set_float_rounding_mode.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| /openbmc/qemu/target/i386/ |
| H A D | ops_sse.h | diff 314d3eff66f41f39191aaca2e5f6e3dc81480c1b Wed Oct 19 07:01:36 CDT 2022 Paolo Bonzini <pbonzini@redhat.com> target/i386: introduce function to set rounding mode from FPCW or MXCSR bits
VROUND, FSTCW and STMXCSR all have to perform the same conversion from
x86 rounding modes to softfloat constants. Since the ISA is consistent
on the meaning of the two-bit rounding modes, extract the common code
into a wrapper for set_float_rounding_mode.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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