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H A D | cacheflush.S | diff 28f07fab26319dacc5675ae01dfc84d82122c59b Fri May 20 07:36:49 CDT 2022 Nicholas Piggin <npiggin@gmail.com> powerpc/vdso: Fix __kernel_sync_dicache sequence with coherent icache
Processors with coherent icache require the sequence sync ; icbi ; isync to entire store->execute coherency. icbi (to any address) must be executed to ensure isync flushes the pipeline. See "POWER9 Processor User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)" for details.
__kernel_sync_dicache is missing icbi for the coherent icache path. Add it.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220520123649.258440-1-npiggin@gmail.com
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