Searched hist:"2736432 ffc30b74fc72858854e62b62253b685ff" (Results 1 – 6 of 6) sorted by relevance
| /openbmc/qemu/target/ppc/ |
| H A D | spr_common.h | diff 2736432ffc30b74fc72858854e62b62253b685ff Sun Jun 18 04:37:07 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement SPRC/SPRD SPRs
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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| H A D | misc_helper.c | diff 2736432ffc30b74fc72858854e62b62253b685ff Sun Jun 18 04:37:07 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement SPRC/SPRD SPRs
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
|
| H A D | cpu_init.c | diff 2736432ffc30b74fc72858854e62b62253b685ff Sun Jun 18 04:37:07 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement SPRC/SPRD SPRs
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
|
| H A D | helper.h | diff 2736432ffc30b74fc72858854e62b62253b685ff Sun Jun 18 04:37:07 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement SPRC/SPRD SPRs
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
|
| H A D | cpu.h | diff 2736432ffc30b74fc72858854e62b62253b685ff Sun Jun 18 04:37:07 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement SPRC/SPRD SPRs
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
|
| H A D | translate.c | diff 2736432ffc30b74fc72858854e62b62253b685ff Sun Jun 18 04:37:07 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement SPRC/SPRD SPRs
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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