Searched hist:"247 c445c0fbd52c77e497ff5bfcf0dceb8afea8d" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | omap4-sar-layout.h | diff 247c445c0fbd52c77e497ff5bfcf0dceb8afea8d Wed May 09 10:08:35 CDT 2012 Santosh Shilimkar <santosh.shilimkar@ti.com> ARM: OMAP5: Add the WakeupGen IP updates
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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| H A D | omap-hotplug.c | diff 247c445c0fbd52c77e497ff5bfcf0dceb8afea8d Wed May 09 10:08:35 CDT 2012 Santosh Shilimkar <santosh.shilimkar@ti.com> ARM: OMAP5: Add the WakeupGen IP updates
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
| H A D | omap-wakeupgen.c | diff 247c445c0fbd52c77e497ff5bfcf0dceb8afea8d Wed May 09 10:08:35 CDT 2012 Santosh Shilimkar <santosh.shilimkar@ti.com> ARM: OMAP5: Add the WakeupGen IP updates
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
| H A D | omap-smp.c | diff 247c445c0fbd52c77e497ff5bfcf0dceb8afea8d Wed May 09 10:08:35 CDT 2012 Santosh Shilimkar <santosh.shilimkar@ti.com> ARM: OMAP5: Add the WakeupGen IP updates
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|