Searched hist:"22 ab3460017cfcfb6b50f05838ad142e08becce5" (Results 1 – 3 of 3) sorted by relevance
/openbmc/qemu/hw/intc/ |
H A D | armv7m_nvic.c | diff 22ab3460017cfcfb6b50f05838ad142e08becce5 Tue Aug 14 11:17:19 CDT 2018 Julia Suvorova <jusual@mail.ru> arm: Add ARMv6-M programmer's model support
Forbid stack alignment change. (CCR) Reserve FAULTMASK, BASEPRI registers. Report any fault as a HardFault. Disable MemManage, BusFault and UsageFault, so they always escalated to HardFault. (SHCSR)
Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180718095628.26442-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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/openbmc/qemu/target/arm/ |
H A D | cpu.c | diff 22ab3460017cfcfb6b50f05838ad142e08becce5 Tue Aug 14 11:17:19 CDT 2018 Julia Suvorova <jusual@mail.ru> arm: Add ARMv6-M programmer's model support
Forbid stack alignment change. (CCR) Reserve FAULTMASK, BASEPRI registers. Report any fault as a HardFault. Disable MemManage, BusFault and UsageFault, so they always escalated to HardFault. (SHCSR)
Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180718095628.26442-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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H A D | helper.c | diff 22ab3460017cfcfb6b50f05838ad142e08becce5 Tue Aug 14 11:17:19 CDT 2018 Julia Suvorova <jusual@mail.ru> arm: Add ARMv6-M programmer's model support
Forbid stack alignment change. (CCR) Reserve FAULTMASK, BASEPRI registers. Report any fault as a HardFault. Disable MemManage, BusFault and UsageFault, so they always escalated to HardFault. (SHCSR)
Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180718095628.26442-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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