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/openbmc/qemu/target/s390x/tcg/
H A Dexcp_helper.cdiff 199c42a6a16ba32b5684e679df949cf29024b0cf Tue Mar 14 21:04:07 CDT 2023 Ilya Leoshkevich <iii@linux.ibm.com> target/s390x: Implement Early Exception Recognition

Generate a specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addressing
mode.

Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20230315020408.384766-3-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
H A Dtranslate.cdiff 199c42a6a16ba32b5684e679df949cf29024b0cf Tue Mar 14 21:04:07 CDT 2023 Ilya Leoshkevich <iii@linux.ibm.com> target/s390x: Implement Early Exception Recognition

Generate a specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addressing
mode.

Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20230315020408.384766-3-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
/openbmc/qemu/target/s390x/
H A Dcpu.hdiff 199c42a6a16ba32b5684e679df949cf29024b0cf Tue Mar 14 21:04:07 CDT 2023 Ilya Leoshkevich <iii@linux.ibm.com> target/s390x: Implement Early Exception Recognition

Generate a specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addressing
mode.

Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20230315020408.384766-3-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
H A Dcpu.cdiff 199c42a6a16ba32b5684e679df949cf29024b0cf Tue Mar 14 21:04:07 CDT 2023 Ilya Leoshkevich <iii@linux.ibm.com> target/s390x: Implement Early Exception Recognition

Generate a specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addressing
mode.

Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20230315020408.384766-3-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>