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| H A D | cs42l42-sdw.c | diff 16838bfbf6e70b7a3381ab302248bd18c085aba5 Fri Jan 27 10:51:11 CST 2023 Stefan Binding <sbinding@opensource.cirrus.com> ASoC: cs42l42: Wait for debounce interval after resume
Since clock stop causes bus reset on Intel controllers, we need
to wait for the debounce interval on resume, to ensure all the
interrupt status registers are set correctly.
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-9-sbinding@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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