Searched hist:"105 b9bb84f4936a5998fcd403a4439e65a84436b" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp.dtsi | diff 105b9bb84f4936a5998fcd403a4439e65a84436b Fri Dec 02 10:23:52 CST 2022 Marek Vasut <marex@denx.de> arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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| H A D | imx8mn.dtsi | diff 105b9bb84f4936a5998fcd403a4439e65a84436b Fri Dec 02 10:23:52 CST 2022 Marek Vasut <marex@denx.de> arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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| H A D | imx8mm.dtsi | diff 105b9bb84f4936a5998fcd403a4439e65a84436b Fri Dec 02 10:23:52 CST 2022 Marek Vasut <marex@denx.de> arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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