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| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | i915_irq.c | diff acd15b6cc20f85bcef9e08b6ed4f142c34791c32 Fri Nov 30 04:24:50 CST 2012 Daniel Vetter <daniel.vetter@ffwll.ch> drm/i915: optimize ilk/snb irq handler
We only need to read/write the south interrupt register if the
corresponding bit is set in the north master interrupt register.
Noticed while reading our interrupt handling code.
Same optimization has already been applied on ivb in
commit 0e43406bcc1868a316eea6012a0a09d992c53521
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed May 9 21:45:44 2012 +0100
drm/i915: Simplify interrupt processing for IvyBridge
We can take advantage that the PCH_IIR is a subordinate register to
reduce one of the required IIR reads, and that we only need to clear
interrupts handled to reduce the writes. And by simply tidying the code
we can reduce the line count and hopefully make it more readable.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff 0e43406bcc1868a316eea6012a0a09d992c53521 Wed May 09 15:45:44 CDT 2012 Chris Wilson <chris@chris-wilson.co.uk> drm/i915: Simplify interrupt processing for IvyBridge
We can take advantage that the PCH_IIR is a subordinate register to
reduce one of the required IIR reads, and that we only need to clear
interrupts handled to reduce the writes. And by simply tidying the code
we can reduce the line count and hopefully make it more readable.
v2: Split out the bugfix from the refactoring.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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