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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_cdclk.c | diff 06f1b06dc5b75b1a4071c905231d40cd74587a18 Mon Jan 30 04:08:06 CST 2023 Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
v2: (Matt)
- Add missing clock steps
- Correct reference clock typo
v3: - Revert to RPL-U subplatform (Jani)
v4: - Remove Bspec reference from code (Jani)
Bspec: 55409
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-3-chaitanya.kumar.borah@intel.com
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