Searched hist:"069 b0d51707721d5ab2001df866b66b82e4c1c35" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/riscv/kernel/ |
| H A D | cpu.c | diff 069b0d51707721d5ab2001df866b66b82e4c1c35 Wed Jun 07 15:28:27 CDT 2023 Conor Dooley <conor.dooley@microchip.com> RISC-V: validate riscv,isa at boot, not during ISA string parsing
Since riscv_fill_hwcap() now only iterates over possible cpus, the
basic validation of whether riscv,isa contains "rv<width>" can be moved
to riscv_early_of_processor_hartid().
Further, "ima" support is required by the kernel, so reject any CPU not
fitting the bill.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230607-guts-blurry-67e711acf328@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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| H A D | cpufeature.c | diff 069b0d51707721d5ab2001df866b66b82e4c1c35 Wed Jun 07 15:28:27 CDT 2023 Conor Dooley <conor.dooley@microchip.com> RISC-V: validate riscv,isa at boot, not during ISA string parsing
Since riscv_fill_hwcap() now only iterates over possible cpus, the
basic validation of whether riscv,isa contains "rv<width>" can be moved
to riscv_early_of_processor_hartid().
Further, "ima" support is required by the kernel, so reject any CPU not
fitting the bill.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230607-guts-blurry-67e711acf328@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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