Searched hist:"0691 bb1b5a1865b3bbc9b7ce6e26eff546abb1cf" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/clk/socfpga/ |
| H A D | clk.h | diff 0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf Mon May 12 12:27:22 CDT 2014 Dinh Nguyen <dinguyen@altera.com> clk: socfpga: add divider registers to the main pll outputs
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.
This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
|
| H A D | clk-periph.c | diff 0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf Mon May 12 12:27:22 CDT 2014 Dinh Nguyen <dinguyen@altera.com> clk: socfpga: add divider registers to the main pll outputs
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.
This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
|
| H A D | clk-gate.c | diff 0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf Mon May 12 12:27:22 CDT 2014 Dinh Nguyen <dinguyen@altera.com> clk: socfpga: add divider registers to the main pll outputs
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.
This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
|