Searched hist:"037602705109 ec2ab96340bea93ad87daa3ac046" (Results 1 – 4 of 4) sorted by relevance
/openbmc/linux/arch/xtensa/boot/boot-elf/ |
H A D | bootstrap.S | diff 037602705109ec2ab96340bea93ad87daa3ac046 Wed Dec 05 14:48:19 CST 2018 Max Filippov <jcmvbkbc@gmail.com> xtensa: don't use l32r opcode directly
xtensa assembler is capable of representing register loads with either movi + addmi, l32r or const16, depending on the core configuration. Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let the assembler relax them.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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/openbmc/linux/arch/xtensa/include/asm/ |
H A D | futex.h | diff 037602705109ec2ab96340bea93ad87daa3ac046 Wed Dec 05 14:48:19 CST 2018 Max Filippov <jcmvbkbc@gmail.com> xtensa: don't use l32r opcode directly
xtensa assembler is capable of representing register loads with either movi + addmi, l32r or const16, depending on the core configuration. Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let the assembler relax them.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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H A D | uaccess.h | diff 037602705109ec2ab96340bea93ad87daa3ac046 Wed Dec 05 14:48:19 CST 2018 Max Filippov <jcmvbkbc@gmail.com> xtensa: don't use l32r opcode directly
xtensa assembler is capable of representing register loads with either movi + addmi, l32r or const16, depending on the core configuration. Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let the assembler relax them.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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/openbmc/linux/arch/xtensa/kernel/ |
H A D | head.S | diff 037602705109ec2ab96340bea93ad87daa3ac046 Wed Dec 05 14:48:19 CST 2018 Max Filippov <jcmvbkbc@gmail.com> xtensa: don't use l32r opcode directly
xtensa assembler is capable of representing register loads with either movi + addmi, l32r or const16, depending on the core configuration. Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let the assembler relax them.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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