Home
last modified time | relevance | path

Searched full:xclk (Results 1 – 25 of 96) sorted by relevance

1234

/openbmc/linux/drivers/media/platform/ti/omap3isp/
H A Disp.c154 * XCLK
159 static void isp_xclk_update(struct isp_xclk *xclk, u32 divider) in isp_xclk_update() argument
161 switch (xclk->id) { in isp_xclk_update()
163 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, in isp_xclk_update()
168 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, in isp_xclk_update()
177 struct isp_xclk *xclk = to_isp_xclk(hw); in isp_xclk_prepare() local
179 omap3isp_get(xclk->isp); in isp_xclk_prepare()
186 struct isp_xclk *xclk = to_isp_xclk(hw); in isp_xclk_unprepare() local
188 omap3isp_put(xclk->isp); in isp_xclk_unprepare()
193 struct isp_xclk *xclk = to_isp_xclk(hw); in isp_xclk_enable() local
[all …]
/openbmc/linux/drivers/media/usb/em28xx/
H A Dem28xx-camera.c323 * need to use a lower xclk frequency. in em28xx_init_camera()
324 * Yet, it would be possible to adjust xclk depending on the in em28xx_init_camera()
328 dev->board.xclk = EM28XX_XCLK_FREQUENCY_4_3MHZ; in em28xx_init_camera()
329 em28xx_write_reg(dev, EM28XX_R0F_XCLK, dev->board.xclk); in em28xx_init_camera()
355 dev->board.xclk = EM28XX_XCLK_FREQUENCY_48MHZ; in em28xx_init_camera()
356 em28xx_write_reg(dev, EM28XX_R0F_XCLK, dev->board.xclk); in em28xx_init_camera()
380 * - adjust bridge xclk in em28xx_init_camera()
398 dev->board.xclk = EM28XX_XCLK_FREQUENCY_24MHZ; in em28xx_init_camera()
399 em28xx_write_reg(dev, EM28XX_R0F_XCLK, dev->board.xclk); in em28xx_init_camera()
H A Dem28xx-input.c389 /* Adjust xclk based on IR table for RC5/NEC tables */ in em2860_ir_change_protocol()
391 dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE; in em2860_ir_change_protocol()
395 dev->board.xclk &= ~EM28XX_XCLK_IR_RC5_MODE; in em2860_ir_change_protocol()
404 em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, dev->board.xclk, in em2860_ir_change_protocol()
418 /* Adjust xclk and set type based on IR table for RC5/NEC/RC6 tables */ in em2874_ir_change_protocol()
420 dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE; in em2874_ir_change_protocol()
424 dev->board.xclk &= ~EM28XX_XCLK_IR_RC5_MODE; in em2874_ir_change_protocol()
429 dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE; in em2874_ir_change_protocol()
440 em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, dev->board.xclk, in em2874_ir_change_protocol()
H A Dem28xx-cards.c674 .xclk = EM28XX_XCLK_FREQUENCY_20MHZ,
710 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ,
719 .xclk = EM28XX_XCLK_FREQUENCY_48MHZ,
1042 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ,
1136 .xclk = EM28XX_XCLK_I2S_MSB_TIMING |
1169 .xclk = EM28XX_XCLK_IR_RC5_MODE |
1195 .xclk = EM28XX_XCLK_IR_RC5_MODE |
1470 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ, /* NEC IR */
1726 .xclk = EM28XX_XCLK_FREQUENCY_10MHZ,
1834 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dovti,ov5640.yaml23 description: XCLK Input Clock
26 const: xclk
105 clock-names = "xclk";
135 clock-names = "xclk";
H A Dov7670.txt9 - clocks: reference to the xclk input clock.
10 - clock-names: should be "xclk".
40 clock-names = "xclk";
H A Dovti,ov7251.yaml25 description: XCLK Input Clock
28 const: xclk
31 description: Frequency of the xclk clock in Hz.
H A Dsony,imx290.yaml45 - const: xclk
48 description: Frequency of the xclk clock in Hz
122 clock-names = "xclk";
H A Dovti,ov5645.yaml20 description: XCLK Input Clock
23 description: Frequency of the xclk clock in Hz.
H A Dsony,imx214.yaml31 description: Reference to the xclk clock.
35 description: Frequency of the xclk clock in Hz.
H A Dst,st-mipid02.yaml35 const: xclk
147 clock-names = "xclk";
H A Dov9650.txt28 clocks = <&xclk>;
/openbmc/linux/drivers/clk/
H A Dclk-max9485.c78 struct clk *xclk; member
268 drvdata->xclk = devm_clk_get(dev, "xclk"); in max9485_i2c_probe()
269 if (IS_ERR(drvdata->xclk)) in max9485_i2c_probe()
270 return PTR_ERR(drvdata->xclk); in max9485_i2c_probe()
272 xclk_name = __clk_get_name(drvdata->xclk); in max9485_i2c_probe()
/openbmc/linux/drivers/media/i2c/
H A Dst-mipid02.c92 struct clk *xclk; member
324 ret = clk_prepare_enable(bridge->xclk); in mipid02_set_power_on()
349 clk_disable_unprepare(bridge->xclk); in mipid02_set_power_on()
356 clk_disable_unprepare(bridge->xclk); in mipid02_set_power_off()
1007 bridge->xclk = devm_clk_get(dev, "xclk"); in mipid02_probe()
1008 if (IS_ERR(bridge->xclk)) { in mipid02_probe()
1009 dev_err(dev, "failed to get xclk\n"); in mipid02_probe()
1010 return PTR_ERR(bridge->xclk); in mipid02_probe()
1013 clk_freq = clk_get_rate(bridge->xclk); in mipid02_probe()
1015 dev_err(dev, "xclk freq must be in 6-27 Mhz range. got %d Hz\n", in mipid02_probe()
H A Dov5645.c93 struct clk *xclk; member
643 clk_disable_unprepare(ov5645->xclk); in ov5645_set_power_off()
659 ret = clk_prepare_enable(ov5645->xclk); in ov5645_set_power_on()
1077 /* get system clock (xclk) */ in ov5645_probe()
1078 ov5645->xclk = devm_clk_get(dev, NULL); in ov5645_probe()
1079 if (IS_ERR(ov5645->xclk)) { in ov5645_probe()
1080 dev_err(dev, "could not get xclk"); in ov5645_probe()
1081 return PTR_ERR(ov5645->xclk); in ov5645_probe()
1086 dev_err(dev, "could not get xclk frequency\n"); in ov5645_probe()
1097 ret = clk_set_rate(ov5645->xclk, xclk_freq); in ov5645_probe()
[all …]
H A Dimx214.c38 struct clk *xclk; member
447 ret = clk_prepare_enable(imx214->xclk); in imx214_power_on()
468 clk_disable_unprepare(imx214->xclk); in imx214_power_off()
968 imx214->xclk = devm_clk_get(dev, NULL); in imx214_probe()
969 if (IS_ERR(imx214->xclk)) { in imx214_probe()
970 dev_err(dev, "could not get xclk"); in imx214_probe()
971 return PTR_ERR(imx214->xclk); in imx214_probe()
974 ret = clk_set_rate(imx214->xclk, IMX214_DEFAULT_CLK_FREQ); in imx214_probe()
976 dev_err(dev, "could not set xclk frequency\n"); in imx214_probe()
H A Dov7251.c133 struct clk *xclk; member
918 ret = clk_prepare_enable(ov7251->xclk); in ov7251_set_power_on()
938 clk_disable_unprepare(ov7251->xclk); in ov7251_set_power_on()
952 clk_disable_unprepare(ov7251->xclk); in ov7251_set_power_off()
1620 /* get system clock (xclk) */ in ov7251_probe()
1621 ov7251->xclk = devm_clk_get_optional(dev, NULL); in ov7251_probe()
1622 if (IS_ERR(ov7251->xclk)) in ov7251_probe()
1623 return dev_err_probe(dev, PTR_ERR(ov7251->xclk), in ov7251_probe()
1624 "could not get xclk"); in ov7251_probe()
1633 if (ret && !ov7251->xclk) in ov7251_probe()
[all …]
H A Dimx290.c230 struct clk *xclk; member
977 /* Set clock parameters based on mode and xclk */ in imx290_start_streaming()
1307 ret = clk_prepare_enable(imx290->xclk); in imx290_power_on()
1317 clk_disable_unprepare(imx290->xclk); in imx290_power_on()
1330 clk_disable_unprepare(imx290->xclk); in imx290_power_off()
1386 dev_err(imx290->dev, "Could not get xclk frequency\n"); in imx290_init_clk()
1404 ret = clk_set_rate(imx290->xclk, xclk_freq); in imx290_init_clk()
1406 dev_err(imx290->dev, "Could not set xclk frequency\n"); in imx290_init_clk()
1538 imx290->xclk = devm_clk_get(dev, "xclk"); in imx290_probe()
1539 if (IS_ERR(imx290->xclk)) in imx290_probe()
[all …]
H A Dimx219.c449 struct clk *xclk; /* system clock to IMX219 */ member
929 ret = clk_prepare_enable(imx219->xclk); in imx219_power_on()
955 clk_disable_unprepare(imx219->xclk); in imx219_power_off()
1254 /* Get system clock (xclk) */ in imx219_probe()
1255 imx219->xclk = devm_clk_get(dev, NULL); in imx219_probe()
1256 if (IS_ERR(imx219->xclk)) { in imx219_probe()
1257 dev_err(dev, "failed to get xclk\n"); in imx219_probe()
1258 return PTR_ERR(imx219->xclk); in imx219_probe()
1261 imx219->xclk_freq = clk_get_rate(imx219->xclk); in imx219_probe()
1263 dev_err(dev, "xclk frequency not supported: %d Hz\n", in imx219_probe()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmaxim,max9485.txt16 - clock-names: Must be set to "xclk"
44 clock-names = "xclk";
/openbmc/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c68 * XCLK The clock rate of the on-chip memory
77 * - MCLK and XCLK use the same FB_DIV
94 * It can be quite hard to calculate XCLK and MCLK if they don't run at the
97 * So this driver uses SCLK to clock the chip and XCLK to clock the memory.
423 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div); in aty_init_pll_ct()
532 printk(KERN_CRIT "atxfb: xclk out of range\n"); in aty_init_pll_ct()
553 printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n", in aty_init_pll_ct()
571 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */ in aty_init_pll_ct()
H A Datyfb_base.c327 static int xclk; variable
383 int pll, mclk, xclk, ecp_max; member
472 par->pll_limits.xclk = aty_chips[i].xclk; in correct_chipset()
500 par->pll_limits.xclk = 67; in correct_chipset()
508 par->pll_limits.xclk = 67; in correct_chipset()
518 par->pll_limits.xclk = 67; in correct_chipset()
526 par->pll_limits.xclk = 67; in correct_chipset()
538 par->pll_limits.xclk = 67; in correct_chipset()
546 par->pll_limits.xclk = 67; in correct_chipset()
2293 static void aty_calc_mem_refresh(struct atyfb_par *par, int xclk) in aty_calc_mem_refresh() argument
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsumo_dpm.c123 u32 xclk = radeon_get_xclk(rdev); in sumo_program_git() local
126 xclk, 16, &p, &u); in sumo_program_git()
134 u32 xclk = radeon_get_xclk(rdev); in sumo_program_grsd() local
137 r600_calculate_u_and_p(1, xclk, 14, &p, &u); in sumo_program_grsd()
154 u32 xclk = radeon_get_xclk(rdev); in sumo_gfx_powergating_initialize() local
173 xclk, 16, &p, &u); in sumo_gfx_powergating_initialize()
179 xclk, 16, &p, &u); in sumo_gfx_powergating_initialize()
318 u32 xclk = radeon_get_xclk(rdev); in sumo_calculate_bsp() local
324 xclk, 16, &pi->bsp, &pi->bsu); in sumo_calculate_bsp()
327 xclk, 16, &pi->pbsp, &pi->pbsu); in sumo_calculate_bsp()
[all …]
H A Dsumo_smc.c145 u32 xclk = radeon_get_xclk(rdev); in sumo_enable_boost_timer() local
150 period = 100 * (xclk / 100 / sumo_power_of_4(unit)); in sumo_enable_boost_timer()
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi21 clock-names = "xclk";

1234