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/openbmc/linux/arch/x86/crypto/
H A Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \ argument
42 movdqa x3, x4; \
44 pxor x4, x0; \
45 pxor x2, x4; \
46 pxor RNOT, x4; \
49 pxor x4, x1; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
53 por x0, x4; \
58 pxor x4, x2; \
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
[all …]
H A Dserpent-sse2-i586-asm_32.S42 #define K(x0, x1, x2, x3, x4, i) \ argument
43 get_key(i, 0, x4); \
46 pxor x4, x0; \
49 get_key(i, 3, x4); \
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
53 movdqa x0, x4; \
55 psrld $(32 - 13), x4; \
56 por x4, x0; \
58 movdqa x2, x4; \
[all …]
H A Dserpent-avx2-asm_64.S51 #define S0_1(x0, x1, x2, x3, x4) \ argument
54 vpxor x2, x3, x4; \
55 vpxor RNOT, x4, x4; \
58 vpxor x4, x1, x1; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
62 vpor x0, x4, x4; \
67 vpxor x4, x2, x2; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
74 vpand tp, x1, x4; \
79 #define S1_2(x0, x1, x2, x3, x4) \ argument
[all …]
H A Dserpent-avx-x86_64-asm_64.S51 #define S0_1(x0, x1, x2, x3, x4) \ argument
54 vpxor x2, x3, x4; \
55 vpxor RNOT, x4, x4; \
58 vpxor x4, x1, x1; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
62 vpor x0, x4, x4; \
67 vpxor x4, x2, x2; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
74 vpand tp, x1, x4; \
79 #define S1_2(x0, x1, x2, x3, x4) \ argument
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-kp-ddc.dts108 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4
109 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4
110 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4
111 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4
112 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4
113 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4
114 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4
115 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4
116 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4
117 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4
[all …]
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0
33 #define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0
40 #define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0
48 #define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0
55 #define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0
62 #define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0
69 #define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0
76 #define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0
83 #define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0
[all …]
H A Dimxrt1050-pinfunc.h21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
28 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
35 #define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
42 #define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
49 #define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
56 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
63 #define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
70 #define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
77 #define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
84 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
[all …]
H A Dimx7d-pinfunc.h18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
43 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
44 #define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
51 #define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
56 #define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
58 #define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
66 #define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
74 #define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
82 #define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
[all …]
/openbmc/linux/drivers/gpu/drm/kmb/
H A Dkmb_regs.h12 #define LCD_CONTROL (0x4 * 0x000)
52 #define LCD_INT_STATUS (0x4 * 0x001)
81 #define LCD_INT_ENABLE (0x4 * 0x002)
82 #define LCD_INT_CLEAR (0x4 * 0x003)
83 #define LCD_LINE_COUNT (0x4 * 0x004)
84 #define LCD_LINE_COMPARE (0x4 * 0x005)
85 #define LCD_VSTATUS (0x4 * 0x006)
91 #define LCD_VSTATUS_COMPARE (0x4 * 0x007)
98 #define LCD_SCREEN_WIDTH (0x4 * 0x008)
99 #define LCD_SCREEN_HEIGHT (0x4 * 0x009)
[all …]
/openbmc/linux/crypto/
H A Dserpent_generic.c41 #define LK(x0, x1, x2, x3, x4, i) ({ \ argument
43 x2 = rol32(x2, 3); x1 ^= x0; x4 = x0 << 3; \
45 x1 = rol32(x1, 1); x3 ^= x4; \
46 x3 = rol32(x3, 7); x4 = x1; \
47 x0 ^= x1; x4 <<= 7; x2 ^= x3; \
48 x0 ^= x3; x2 ^= x4; x3 ^= k[4*i+3]; \
53 #define KL(x0, x1, x2, x3, x4, i) ({ \ argument
56 x4 = x1; x2 ^= x3; x0 ^= x3; \
57 x4 <<= 7; x0 ^= x1; x1 = ror32(x1, 1); \
58 x2 ^= x4; x3 = ror32(x3, 7); x4 = x0 << 3; \
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddmc.h17 unsigned char res1[0x4];
130 unsigned char res2[0x4];
133 unsigned char res3[0x4];
137 unsigned char resr5[0x4];
139 unsigned char res6[0x4];
141 unsigned char res7[0x4];
143 unsigned char res8[0x4];
145 unsigned char res9[0x4];
147 unsigned char res10[0x4];
149 unsigned char res11[0x4];
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h52 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0
58 #define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0
66 #define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0
76 #define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0
81 #define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0
158 #define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0
159 #define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0
164 #define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1
165 #define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0
170 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0
[all …]
H A Dimx93-pinfunc.h16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
24 #define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0
30 #define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0
37 #define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0
45 #define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0
53 #define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0
61 #define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0
69 #define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0
77 #define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0
[all …]
H A Dimx8mn-pinfunc.h57 …ne MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0
65 …ne MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0
77 …ne MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2
81 …ne MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2
87 …ne MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0
93 …ne MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1
99 …ne MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1
161 …ne MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0
162 …ne MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4
166 …ne MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_devdis.h30 { "ddr", 0x4, 0x80000000 }, /* DDR */
31 { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */
32 { "ifc", 0x4, 0x800000 }, /* IFC */
33 { "gpio", 0x4, 0x400000 }, /* GPIO */
34 { "dbg", 0x4, 0x200000 }, /* DBG */
35 { "can1", 0x4, 0x80000 }, /* FlexCAN1 */
36 { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */
37 { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */
38 { "secmon", 0x4, 0x4000 }, /* Security Monitor */
39 { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sl-pinfunc.h21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
29 #define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0
37 #define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0
44 #define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0
52 #define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0
59 #define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0
66 #define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0
73 #define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0
80 #define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0
87 #define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0
[all …]
H A Dimx7d-pinfunc.h22 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
47 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
48 #define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
55 #define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
60 #define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
62 #define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
70 #define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
78 #define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
86 #define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxgene-pci-msi.txt28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
35 <0x0 0x17 0x4>
36 <0x0 0x18 0x4>
37 <0x0 0x19 0x4>
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear13xx.dtsi88 interrupts = <0 28 0x4>;
95 interrupts = <0 29 0x4>;
104 interrupts = <0 19 0x4>;
121 interrupts = <0 59 0x4>;
144 interrupts = <0 20 0x4>,
145 <0 21 0x4>,
146 <0 22 0x4>,
147 <0 23 0x4>;
155 interrupts = <0 33 0x4>,
156 <0 34 0x4>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h41 #define BUS_CNTL__PMI_IO_DIS_MASK 0x4
46 #define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
69 #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
89 #define BX_RESET_EN__STY_RESET_EN_MASK 0x4
99 #define HW_DEBUG__HW_02_DEBUG_MASK 0x4
104 #define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
184 #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
197 #define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
202 #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
231 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-xp.c46 MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
50 MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
54 MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)),
58 MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)),
62 MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)),
66 MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)),
70 MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)),
74 MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)),
78 MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)),
82 MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)),
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dtscs454.h19 #define R_IRQSTAT VIRT_ADDR(0x0, 0x4)
71 #define R_HSDDELAY VIRT_ADDR(0x1, 0x4)
103 #define R_DCCTL VIRT_ADDR(0x2, 0x4)
129 #define R_SPKCRWDH VIRT_ADDR(0x3, 0x4)
179 #define R_DACEQFILT VIRT_ADDR(0x4, 0x1)
180 #define R_DACCRWDL VIRT_ADDR(0x4, 0x2)
181 #define R_DACCRWDM VIRT_ADDR(0x4, 0x3)
182 #define R_DACCRWDH VIRT_ADDR(0x4, 0x4)
183 #define R_DACCRRDL VIRT_ADDR(0x4, 0x5)
184 #define R_DACCRRDM VIRT_ADDR(0x4, 0x6)
[all …]
/openbmc/linux/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi268 csr-offset = <0x4>;
282 csr-offset = <0x4>;
296 csr-offset = <0x4>;
309 csr-offset = <0x4>;
322 csr-offset = <0x4>;
335 csr-offset = <0x4>;
431 interrupts = < 0x0 0x10 0x4
432 0x0 0x11 0x4
433 0x0 0x12 0x4
434 0x0 0x13 0x4
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
39 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
48 #define PX30_PLL_CON(x) ((x) * 0x4)
49 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
50 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
53 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
63 #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
64 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
65 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
68 #define RV1108_PLL_CON(x) ((x) * 0x4)
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dhardware.c29 {HPHW_NPROC,0x01,0x4,0x0,"Indigo (840, 930)"},
30 {HPHW_NPROC,0x8,0x4,0x01,"Firefox(825,925)"},
31 {HPHW_NPROC,0xA,0x4,0x01,"Top Gun (835,834,935,635)"},
32 {HPHW_NPROC,0xB,0x4,0x01,"Technical Shogun (845, 645)"},
33 {HPHW_NPROC,0xF,0x4,0x01,"Commercial Shogun (949)"},
34 {HPHW_NPROC,0xC,0x4,0x01,"Cheetah (850, 950)"},
35 {HPHW_NPROC,0x80,0x4,0x01,"Cheetah (950S)"},
36 {HPHW_NPROC,0x81,0x4,0x01,"Jaguar (855, 955)"},
37 {HPHW_NPROC,0x82,0x4,0x01,"Cougar (860, 960)"},
38 {HPHW_NPROC,0x83,0x4,0x13,"Panther (865, 870, 980)"},
[all …]

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