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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
[all …]
/openbmc/u-boot/drivers/power/pmic/
H A DKconfig2 bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC)"
4 ---help---
5 This config enables the driver-model PMIC support.
6 UCLASS_PMIC - designed to provide an I/O interface for PMIC devices.
7 For the multi-function PMIC devices, this can be used as parent I/O
9 for read/write. For detailed description, please refer to the files:
10 - 'drivers/power/pmic/pmic-uclass.c'
11 - 'include/power/pmic.h'
17 ---help---
21 U-Boot proper.
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/openbmc/openbmc/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/
H A Dibm.json40 "Enable Secure Boot": false,
41 "User region ECC enable": true,
42 "Secure Region ECC enable": false,
52 "Write Protect: Secure Region": true,
53 "Write Protect: User region": true,
54 "Write Protect: Configure region": true,
55 "Write Protect: OTP strap region": true,
57 "Enable image encryption": false,
58 "Enable write Protect of OTP key retire bits": false,
60 "OTP memory lock enable": false,
[all …]
H A Dips.json47 "Enable Secure Boot": false,
48 "User region ECC enable": true,
49 "Secure Region ECC enable": false,
59 "Write Protect: Secure Region": true,
60 "Write Protect: User region": true,
61 "Write Protect: Configure region": true,
62 "Write Protect: OTP strap region": true,
64 "Enable image encryption": false,
65 "Enable write Protect of OTP key retire bits": false,
67 "OTP memory lock enable": false,
[all …]
/openbmc/linux/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Write Register 0 */
37 /* Write Register 1 */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
52 /* Write Register #2 (Interrupt Vector) */
54 /* Write Register 3 */
56 #define RxENABLE 0x1 /* Rx Enable */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-xdata1 What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
5 Description: Allows the user to enable the PCIe traffic generator which
6 will create write TLPs frames - from the Root Complex to the
10 Write y/1/on to enable, n/0/off to disable
13 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
15 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
21 cat /sys/class/misc/dw-xdata-pcie.<device>/write
24 The file is read and write.
26 What: /sys/class/misc/dw-xdata-pcie.<device>/read
30 Description: Allows the user to enable the PCIe traffic generator which
[all …]
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
81 * Controller (UDC) Control Register (read/write).
83 * Controller (UDC) Address Register (read/write).
86 * (read/write).
89 * (read/write).
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
58 * Desc: Execute Write leveling phase by HW
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
103 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
107 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
30 /* Write Register 0 */
61 /* Write Register 1 */
63 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
75 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
77 /* Write Register #2 (Interrupt Vector) */
79 /* Write Register 3 */
81 #define RxENAB 0x1 /* Rx Enable */
[all …]
H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
59 /* Write Register 0 (Command) */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
103 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
105 /* Write Register 2 (Interrupt Vector) */
[all …]
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
38 /* Write Register 0 */
69 /* Write Register 1 */
71 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
89 #define RxENAB 0x1 /* Rx Enable */
[all …]
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
/openbmc/u-boot/drivers/rtc/
H A Dimxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009-2012 ADVANSEE
6 * Based on the Linux rtc-imxdi.c driver, which is:
7 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
21 #include <asm/arch/imx-regs.h>
32 u32 dier; /* Interrupt Enable Reg */
35 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
37 #define DCR_TCE (1 << 3) /* Time Counter Enable */
39 #define DSR_WBF (1 << 10) /* Write Busy Flag */
40 #define DSR_WNF (1 << 9) /* Write Next Flag */
[all …]
/openbmc/u-boot/cmd/
H A Dotp_info.h7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
34 { 0, 1, 1, "Enable Secure Boot" },
36 { 1, 1, 1, "Enable boot from eMMC" },
38 { 2, 1, 1, "Enable Boot from debug SPI" },
39 { 3, 1, 0, "Enable ARM CM3" },
42 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" },
61 { 16, 1, 0, "Enable ARM JTAG debug" },
65 { 18, 1, 0, "Enable debug interfaces 0" },
[all …]
/openbmc/linux/drivers/infiniband/ulp/rtrs/
H A Drtrs-clt-stats.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2014 - 2018 ProfitBricks GmbH. All rights reserved.
6 * Copyright (c) 2018 - 2019 1&1 IONOS Cloud GmbH. All rights reserved.
7 * Copyright (c) 2019 - 2020 1&1 IONOS SE. All rights reserved.
12 #include "rtrs-clt.h"
16 struct rtrs_clt_path *clt_path = to_clt_path(con->c.path); in rtrs_clt_update_wc_stats()
17 struct rtrs_clt_stats *stats = clt_path->stats; in rtrs_clt_update_wc_stats()
22 s = get_cpu_ptr(stats->pcpu_stats); in rtrs_clt_update_wc_stats()
23 if (con->cpu != cpu) { in rtrs_clt_update_wc_stats()
24 s->cpu_migr.to++; in rtrs_clt_update_wc_stats()
[all …]
/openbmc/u-boot/include/
H A DSA-1100.h2 * FILE SA-1100.h
8 * System StrongARM SA-1100
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
15 * Language-specific definitions are selected by the
33 #include <asm/arch-sa1100/bitfield.h>
185 * Controller (UDC) Control Register (read/write).
187 * Controller (UDC) Address Register (read/write).
190 * (read/write).
193 * (read/write).
[all …]
H A Dmisc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * misc_read() - Read the device to buffer, optional.
16 * Return: number of bytes read if OK (may be 0 if EOF), -ve on error
21 * misc_write() - Write buffer to the device, optional.
23 * @offset: offset to write the device
25 * @size: data size in bytes to write the device
27 * Return: number of bytes written if OK (may be < @size), -ve on error
32 * misc_ioctl() - Assert command to the device, optional.
37 * Return: 0 if OK, -ve on error
42 * misc_call() - Send a message to the device and wait for a response.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
[all …]
/openbmc/linux/include/linux/
H A Dfsl_ifc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
35 * CSPR - Chip Select Property Register
47 /* Write Protect */
69 (__ilog2(n) - IFC_AMASK_SHIFT))
74 /* Enable ECC Encoder */
81 /* Enable ECC Decoder */
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
111 /* Time for Read Enable High to Output High Impedance */
[all …]
/openbmc/u-boot/include/usb/
H A Dulpi.h1 /* SPDX-License-Identifier: GPL-2.0 */
40 * @ulpi_vp - structure containing ULPI viewport data
48 * @speed - ULPI_FC_HIGH_SPEED, ULPI_FC_FULL_SPEED (default),
55 * Enable/disable VBUS.
56 * @ext_power - external VBUS supply is used (default is false)
57 * @ext_indicator - external VBUS over-current indicator is used
65 * @external - external VBUS over-current indicator is used
66 * @passthru - disables ANDing of internal VBUS comparator
68 * @complement - inverts the external VBUS input
74 * Enable/disable pull-down resistors on D+ and D- USB lines.
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm54xxacr.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define CACR_DEC 0x80000000 /* Enable data cache */
13 #define CACR_DWP 0x40000000 /* Data write protection */
14 #define CACR_DESB 0x20000000 /* Enable data store buffer */
17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
22 #define CACR_BEC 0x00080000 /* Enable branch cache */
24 #define CACR_IEC 0x00008000 /* Enable instruction cache */
30 #define CACR_EUSP 0x00000020 /* Enable separate user a7 */
34 #define ACR_ENABLE 0x00008000 /* Enable address */
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
[all …]
H A Dmcfmmu.h2 * mcfmmu.h -- definitions for the ColdFire v4e MMU
35 #define MMUCR_EN 0x00000001 /* Virtual mode enable */
44 #define MMUOR_WR 0x00000000 /* TLB access write */
47 #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
48 #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
58 #define MMUSR_WF 0x00000008 /* Write access fault */
63 * MMU Read/Write Tag register.
73 * MMU Read/Write Data register.
76 #define MMUDR_X 0x00000004 /* Execute access enable */
77 #define MMUDR_W 0x00000008 /* Write access enable */
[all …]
/openbmc/linux/drivers/media/i2c/adv748x/
H A Dadv748x-core.c1 // SPDX-License-Identifier: GPL-2.0+
21 #include <linux/v4l2-dv-timings.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-ioctl.h>
31 /* -----------------------------------------------------------------------------
63 if (!state->i2c_clients[region]) in adv748x_configure_regmap()
64 return -ENODEV; in adv748x_configure_regmap()
[all …]
/openbmc/linux/drivers/char/xilinx_hwicap/
H A Dfifo_icap.c24 * (c) Copyright 2007-2008 Xilinx Inc.
28 * with this program; if not, write to the Free Software Foundation, Inc.,
36 #define XHI_GIER_OFFSET 0x1C /* Device Global Interrupt Enable Reg */
38 #define XHI_IPIER_OFFSET 0x28 /* Interrupt Enable Register */
39 #define XHI_WF_OFFSET 0x100 /* Write FIFO */
44 #define XHI_WFV_OFFSET 0x114 /* Write FIFO Vacancy Register */
47 /* Device Global Interrupt Enable Register (GIER) bit definitions */
49 #define XHI_GIER_GIE_MASK 0x80000000 /* Global Interrupt enable Mask */
52 * HwIcap Device Interrupt Status/Enable Registers
56 * write.
[all …]

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