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/openbmc/linux/drivers/watchdog/
H A Dwd501p.h1 /* SPDX-License-Identifier: GPL-1.0+ */
25 #define WDT_BUZZER (io+6) /* PCI only: rd=disable, wr=enable */
30 #define WDT_CLOCK (io+12) /* COUNT2: rd=16.67MHz, wr=2.0833MHz */
32 #define WDT_OPTONOTRST (io+13) /* wr=enable, rd=disable */
34 #define WDT_OPTORST (io+14) /* wr=enable, rd=disable */
36 #define WDT_PROGOUT (io+15) /* wr=enable, rd=disable */
39 #define WDC_SR_WCCR 1 /* Active low */ /* X X X */
40 #define WDC_SR_TGOOD 2 /* X X - */
43 #define WDC_SR_FANGOOD 16 /* X - - */
44 #define WDC_SR_PSUOVER 32 /* Active low */ /* X X - */
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/openbmc/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,fimd.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,s3c2443-fimd
19 - samsung,s3c6400-fimd
20 - samsung,s5pv210-fimd
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H A Dsamsung,exynos7-decon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
22 const: samsung,exynos7-decon
27 clock-names:
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/openbmc/linux/net/smc/
H A Dsmc_core.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Shared Memory Communications over RDMA (SMC-R) and RoCE
29 * also is the default value for SMC-R v1 and v2.0
32 * SMC-R v2.1 and later negotiation, vendors or
34 * 16-255 as needed.
52 SMC_LNK_ACTIVE, /* link is active */
95 struct smc_ib_device *smcibdev; /* ib-device */
96 u8 ibport; /* port - values 1 | 2 */
103 struct smc_wr_buf *wr_tx_bufs; /* WR send payload buffers */
104 struct ib_send_wr *wr_tx_ibs; /* WR send meta data */
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/openbmc/linux/drivers/perf/
H A Dxgene_pmu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * APM X-Gene SoC PMU (Performance Monitor Unit)
81 #define GET_CNTR(ev) (ev->hw.idx)
82 #define GET_EVENTID(ev) (ev->hw.config & 0xFFULL)
83 #define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL)
84 #define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL)
173 return sysfs_emit(buf, "%s\n", (char *) eattr->var); in xgene_pmu_format_show()
183 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"),
184 XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"),
189 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"),
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/openbmc/linux/drivers/net/ethernet/8390/
H A D8390.h1 /* SPDX-License-Identifier: GPL-1.0+ */
6 * under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
21 /* The 8390 specific per-packet-header format. */
34 /* Without I/O delay - non ISA or later chips */
70 /* You have one of these per-board */
85 unsigned word16:1; /* We have the 16-bit (vs 8-bit)
88 unsigned bigendian:1; /* 16-bit big endian mode. Do NOT
91 unsigned txing:1; /* Transmit Active */
93 unsigned dmaing:1; /* Remote DMA Active */
98 short tx1, tx2; /* Packet lengths for ping-pong tx. */
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
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H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
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H A Domap3-overo-base.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
17 led-controller {
18 compatible = "pwm-leds";
20 led-1 {
23 max-brightness = <127>;
24 linux,default-trigger = "mmc0";
29 compatible = "ti,omap-twl4030";
37 compatible = "regulator-fixed";
38 regulator-name = "hsusb2_vbus";
39 regulator-min-microvolt = <5000000>;
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H A Ddra7-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-evm-common.dtsi"
9 #include "dra74x-mmc-iodelay.dtsi"
13 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
20 evm_12v0: fixedregulator-evm_12v0 {
22 compatible = "regulator-fixed";
23 regulator-name = "evm_12v0";
24 regulator-min-microvolt = <12000000>;
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H A Dam3517-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on am3517-evm.dts
11 cpu0-supply = <&vdd_core_reg>;
16 compatible = "regulator-fixed";
17 regulator-name = "wl1271_buf";
18 regulator-min-microvolt = <1800000>;
19 regulator-max-microvolt = <1800000>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&wl12xx_buffer_pins>;
23 regulator-always-on;
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/openbmc/linux/drivers/scsi/csiostor/
H A Dcsio_scsi.c4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
76 * csio_scsi_match_io - Match an ioreq with the given SCSI level data.
88 switch (sld->level) { in csio_scsi_match_io()
93 return ((ioreq->lnode == sld->lnode) && in csio_scsi_match_io()
94 (ioreq->rnode == sld->rnode) && in csio_scsi_match_io()
95 ((uint64_t)scmnd->device->lun == sld->oslun)); in csio_scsi_match_io()
98 return ((ioreq->lnode == sld->lnode) && in csio_scsi_match_io()
99 (ioreq->rnode == sld->rnode)); in csio_scsi_match_io()
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/openbmc/linux/arch/sparc/kernel/
H A Dwof.S1 /* SPDX-License-Identifier: GPL-2.0 */
49 /* On a 7-window Sparc the boot code patches spnwin_*
66 /* Datum current_thread_info->uwinmask contains at all times a bitmask
67 * where if any user windows are active, at least one bit will
68 * be set in to mask. If no user windows are active, the bitmask
82 * newwim = ((%wim>>1) | (%wim<<(nwindows - 1)));
99 /* See if any user windows are active in the set. */
111 wr %glob_tmp, 0x0, %wim ! set new %wim, this is safe now
122 wr %t_psr, 0x0, %psr ! restore condition codes in %psr
148 wr %glob_tmp, 0x0, %wim ! Now it is safe to set new %wim
[all …]
H A Dwuf.S1 /* SPDX-License-Identifier: GPL-2.0 */
44 /* Datum current_thread_info->uwinmask contains at all times a bitmask
45 * where if any user windows are active, at least one bit will
46 * be set in to mask. If no user windows are active, the bitmask
53 * 1 2 3 4 <-- Window number
54 * ----------
55 * T O W I <-- Symbolic name
73 /* On 7-window Sparc the boot code patches fnwin_patch1
93 wr %twin_tmp1, 0x0, %wim /* Make window 'I' invalid */
122 wr %t_psr, 0x0, %psr
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-mlc.txt4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH
17 - nxp,rd_low: RD_LOW
18 - nxp,wr_high: WR_HIGH
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam335x-brppt1-nand.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * http://www.br-automation.com
7 /dts-v1/;
15 fset: factory-settings {
16 bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
18 order-no = "6PPT30 (NAND)";
19 hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
20 serial-no = "0";
21 device-id = <0x0>;
22 parent-id = <0x0>;
[all …]
H A Darmada-385-atl-x530.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/gpio.h>
4 #include "armada-385.dtsi"
11 stdout-path = "serial0:115200n8";
30 pcie-mem-aperture = <0xa0000000 0x40000000>;
33 eco-button-interrupt {
34 compatible = "atl,eco-button-interrupt";
35 eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
38 board-reset {
40 /* Physical board layout of reset pin is active-low but for the
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H A Dam437x-gp-evm.dts2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/pinctrl/am43xx.h>
15 #include <dt-bindings/pwm/pwm.h>
16 #include <dt-bindings/gpio/gpio.h>
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
28 stdout-path = &uart0;
29 tick-timer = &timer2;
32 vmmcsd_fixed: fixedregulator-sd {
33 compatible = "regulator-fixed";
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H A Ddra7-evm.dts2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include "dra7-evm-common.dtsi"
12 #include "dra74x-mmc-iodelay.dtsi"
16 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
23 evm_1v8_sw: fixedregulator-evm_1v8 {
24 compatible = "regulator-fixed";
25 regulator-name = "evm_1v8";
26 vin-supply = <&smps9_reg>;
27 regulator-min-microvolt = <1800000>;
[all …]
H A Dam3517-som.dtsi4 * Based on am3517-evm.dts
14 cpu0-supply = <&vdd_core_reg>;
19 compatible = "regulator-fixed";
20 regulator-name = "wl1271_buf";
21 regulator-min-microvolt = <1800000>;
22 regulator-max-microvolt = <1800000>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&wl12xx_buffer_pins>;
26 regulator-always-on;
27 vin-supply = <&vdd_1v8_reg>;
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_spd.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Based on JEDEC Standard No. 21-C, 4.1.2.L-4:
18 /* block 1: module specific parameters sub-block */
20 /* block 1: hybrid memory parameters sub-block */
185 unsigned char byte_28; /* min active to precharge delay time (t ras min), l-s-byte, mtb */
186 unsigned char byte_29; /* min active to active/refresh delay time (t rc min), l-s-byte, mtb */
187 unsigned char byte_30; /* min refresh recovery delay time (t rfc1 min), l-s-byte, mtb */
188 unsigned char byte_31; /* min refresh recovery delay time (t rfc1 min), m-s-byte, mtb */
189 unsigned char byte_32; /* min refresh recovery delay time (t rfc2 min), l-s-byte, mtb */
190 unsigned char byte_33; /* min refresh recovery delay time (t rfc2 min), m-s-byte, mtb */
[all …]
/openbmc/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
7 compatible = "cavium,octeon-3860";
8 #address-cells = <2>;
9 #size-cells = <2>;
10 interrupt-parent = <&ciu>;
13 compatible = "simple-bus";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 ciu: interrupt-controller@1070000000000 {
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/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dbootbus.txt7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
22 u32 t_ras; /* Active to precharge command period */
23 u32 t_srex; /* Self-refresh exit time */
26 u32 t_rc; /* Active to active command period */
27 u32 t_rfc; /* Auto-refresh period */
28 u32 t_xsr; /* Exit self-refresh to active command time */
29 u32 t_rrd; /* Active bank A to active bank B latency */
30 u32 t_mrd; /* Load mode register to active command time */
33 u32 extended_wait; /* time for static memory rd/wr transfers */
71 #define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
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