Home
last modified time | relevance | path

Searched +full:wp +full:- +full:controller (Results 1 – 25 of 488) sorted by relevance

12345678910>>...20

/openbmc/linux/sound/hda/
H A Dhdac_controller.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio controller helpers
19 for (timeout = 1000; timeout > 0; timeout--) { in azx_clear_corbrp()
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", in azx_clear_corbrp()
29 for (timeout = 1000; timeout > 0; timeout--) { in azx_clear_corbrp()
35 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", in azx_clear_corbrp()
40 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
41 * @bus: HD-audio core bus
45 WARN_ON_ONCE(!bus->rb.area); in snd_hdac_bus_init_cmd_io()
47 spin_lock_irq(&bus->reg_lock); in snd_hdac_bus_init_cmd_io()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC Controller Common Properties
10 - Ulf Hansson <ulf.hansson@linaro.org>
17 It is possible to assign a fixed index mmcN to an MMC host controller
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
[all …]
H A Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
3 The Enhanced Secure Digital Host Controller provides an interface
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
[all …]
H A Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
16 The Enhanced Secure Digital Host Controller on Freescale i.MX family
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
[all …]
H A Dk3-dw-mshc.txt2 Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
10 extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
[all …]
H A Dsunplus,mmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus MMC Controller
11 - Tony Huang <tonyhuang.sunplus@gmail.com>
12 - Li-hao Kuo <lhjeff911@gmail.com>
15 - $ref: mmc-controller.yaml
20 - sunplus,sp7021-mmc
35 - compatible
36 - reg
[all …]
H A Datmel-hsmci.txt3 This controller on atmel products provides an interface for MMC, SD and SDIO
7 by mmc.txt and the properties used by the atmel-mci driver.
12 - compatible: should be "atmel,hsmci"
13 - #address-cells: should be one. The cell is the slot id.
14 - #size-cells: should be zero.
15 - at least one slot node
16 - clock-names: tuple listing input clock names.
18 - clocks: phandles to input clocks.
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
16 registers and for its data input/output buffer. On some SoCs, this controller
20 This controller was originally designed for STB SoCs (BCM7xxx) but is now
[all …]
H A Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs NAND controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
[all …]
/openbmc/u-boot/doc/device-tree-bindings/nand/
H A Dnvidia,tegra20-nand.txt2 ----------
5 U-Boot. There should not be Linux-specific or U-Boot specific binding, just
12 - compatible : Should be "manufacturer,device", "nand-flash"
14 This node should sit inside its controller.
17 Nvidia NAND Controller
18 ----------------------
20 The device node for a NAND flash controller is as follows:
24 nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
26 nvidia,nand-width : bus width of the NAND device in bits
28 - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
35 mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-rex.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 stdout-path = &uart1;
16 reg_3p3v: regulator-3p3v {
17 compatible = "regulator-fixed";
18 regulator-name = "3P3V";
19 regulator-min-microvolt = <3300000>;
20 regulator-max-microvolt = <3300000>;
21 regulator-always-on;
[all …]
H A Dimx50-kobo-aura.dts1 // SPDX-License-Identifier: GPL-2.0+
4 // The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B.
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
16 stdout-path = "serial1:115200n8";
24 gpio-leds {
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_leds>;
[all …]
H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 power-supply = <&reg_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
33 gpio_buttons: gpio-keys {
[all …]
H A Dimx6sx-sabreauto.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
11 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_led>;
23 led-user {
26 linux,default-trigger = "heartbeat";
30 vcc_sd3: regulator-vcc-sd3 {
31 compatible = "regulator-fixed";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sx-sabreauto.dts9 /dts-v1/;
15 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
27 compatible = "regulator-fixed";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_vcc_sd3>;
31 regulator-name = "VCC_SD3";
32 regulator-min-microvolt = <3000000>;
[all …]
H A Drk3328-evb.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
11 compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
14 stdout-path = &uart2;
17 gmac_clkin: external-gmac-clock {
18 compatible = "fixed-clock";
19 clock-frequency = <125000000>;
20 clock-output-names = "gmac_clkin";
21 #clock-cells = <0>;
24 vcc3v3_sdmmc: sdmmc-pwren {
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-pogoplug-series-4.dts1 // SPDX-License-Identifier: GPL-2.0
3 * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4
10 /dts-v1/;
13 #include "kirkwood-6192.dtsi"
14 #include <dt-bindings/input/linux-event-codes.h>
18 compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192",
27 stdout-path = "uart0:115200n8";
31 compatible = "gpio-keys";
32 #address-cells = <1>;
33 #size-cells = <0>;
[all …]
/openbmc/linux/sound/pci/lola/
H A Dlola.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for Digigram Lola PCI-e boards
11 #include <linux/dma-mapping.h>
34 /* Lola-specific options */
40 [0 ... (SNDRV_CARDS - 1)] = LOLA_GRANULARITY_MAX
45 [0 ... (SNDRV_CARDS - 1) ] = 16000
70 * pseudo-codec read/write via CORB/RIRB
78 int ret = -EIO; in corb_send_verb()
80 chip->last_cmd_nid = nid; in corb_send_verb()
81 chip->last_verb = verb; in corb_send_verb()
[all …]
/openbmc/linux/drivers/bus/mhi/host/
H A Dinit.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
10 #include <linux/dma-direction.h>
11 #include <linux/dma-mapping.h>
59 [MHI_PM_STATE_M3_ENTER] = "M?->M3",
61 [MHI_PM_STATE_M3_EXIT] = "M3->M0",
88 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; in serial_number_show()
91 mhi_cntrl->serial_number); in serial_number_show()
100 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; in oem_pk_hash_show()
103 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++) in oem_pk_hash_show()
[all …]
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0
17 struct mhi_controller *mhi_cntrl = m->private; in mhi_debugfs_states_show()
21 to_mhi_pm_state_str(mhi_cntrl->pm_state), in mhi_debugfs_states_show()
23 mhi_state_str(mhi_cntrl->dev_state), in mhi_debugfs_states_show()
24 TO_MHI_EXEC_STR(mhi_cntrl->ee), in mhi_debugfs_states_show()
25 mhi_cntrl->wake_set ? "true" : "false"); in mhi_debugfs_states_show()
28 seq_printf(m, "M0: %u M2: %u M3: %u", mhi_cntrl->M0, mhi_cntrl->M2, in mhi_debugfs_states_show()
29 mhi_cntrl->M3); in mhi_debugfs_states_show()
32 atomic_read(&mhi_cntrl->dev_wake), in mhi_debugfs_states_show()
33 atomic_read(&mhi_cntrl->pending_pkts)); in mhi_debugfs_states_show()
[all …]
/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-nezha.dts1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
7 * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
8 * directly to pads on the SoC, others come from an 8-bit pcf857x IO
10 * one set for the pcf857x, and one set for the pio controller.
12 * Lines which are routed to the 40-pin header are named as follows:
15 * <pin#> is the actual pin number of the 40-pin header
20 * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
23 #include <dt-bindings/gpio/gpio.h>
24 #include <dt-bindings/input/input.h>
[all …]
/openbmc/qemu/hw/nvme/
H A Dtrace-events2 pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u"
56 pci_nvme_identify_ctrl(void) "identify controller"
57 pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=0x%"PRIx8""
61 pci_nvme_identify_pri_ctrl_cap(uint16_t cntlid) "identify primary controller capabilities cntlid=%"…
62 pci_nvme_identify_sec_ctrl_list(uint16_t cntlid, uint8_t numcntl) "identify secondary controller li…
96 pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=0x%"PRIx64""
102 pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded"
103 pci_nvme_mmio_stopped(void) "cleared controller enable bit"
129 pci_nvme_err_cfs(void) "controller fatal status"
146 …not_at_wp(uint64_t slba, uint64_t zone, uint64_t wp) "writing at slba=%"PRIu64", zone=%"PRIu64", b…
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
[all …]

12345678910>>...20