/openbmc/linux/Documentation/devicetree/bindings/net/dsa/ |
H A D | nxp,sja1105.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at 16 - Vladimir Oltean <vladimir.oltean@nxp.com> 21 - nxp,sja1105e 22 - nxp,sja1105t 23 - nxp,sja1105p 24 - nxp,sja1105q 25 - nxp,sja1105r [all …]
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H A D | microchip,lan937x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - UNGLinuxDriver@microchip.com 13 - $ref: dsa.yaml#/$defs/ethernet-ports 18 - microchip,lan9370 19 - microchip,lan9371 20 - microchip,lan9372 21 - microchip,lan9373 22 - microchip,lan9374 [all …]
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/openbmc/linux/arch/riscv/boot/dts/starfive/ |
H A D | jh7110-starfive-visionfive-2-v1.3b.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include "jh7110-starfive-visionfive-2.dtsi" 12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; 16 starfive,tx-use-rgmii-clk; 17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; 18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; 22 starfive,tx-use-rgmii-clk; 23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; 24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; [all …]
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H A D | jh7110-starfive-visionfive-2-v1.2a.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include "jh7110-starfive-visionfive-2.dtsi" 12 compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; 16 phy-mode = "rmii"; 17 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>, 19 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>, 24 rx-internal-delay-ps = <1900>; 25 tx-internal-delay-ps = <1350>;
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Neil Armstrong <neil.armstrong@linaro.org> 12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 20 - amlogic,meson6-dwmac 21 - amlogic,meson8b-dwmac 22 - amlogic,meson8m2-dwmac 23 - amlogic,meson-gxbb-dwmac [all …]
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H A D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - David S. Miller <davem@davemloft.net> 20 local-mac-address: 23 $ref: /schemas/types.yaml#/definitions/uint8-array 27 mac-address: 32 local-mac-address property. 33 $ref: /schemas/types.yaml#/definitions/uint8-array [all …]
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H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Sae <frank.sae@motor-comm.com> 13 - $ref: ethernet-phy.yaml# 18 - ethernet-phy-id4f51.e91a 19 - ethernet-phy-id4f51.e91b 21 rx-internal-delay-ps: 23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. [all …]
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H A D | ti,dp83822.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Andrew Davis <afd@ti.com> 14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It 16 data over standard, twisted-pair cables or to connect to an external, 17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to 24 - $ref: ethernet-phy.yaml# 30 ti,link-loss-low: 39 ti,fiber-mode: [all …]
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H A D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+ 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alexandru Tachici <alexandru.tachici@analog.com> 16 - $ref: ethernet-phy.yaml# 19 adi,rx-internal-delay-ps: 21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. 26 adi,tx-internal-delay-ps: 28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with [all …]
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H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - $ref: ethernet-controller.yaml# 14 - Andrew Davis <afd@ti.com> 18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX 19 and 1000BASE-T Ethernet protocols. 34 nvmem-cells: 40 nvmem-cell-names: 42 - const: io_impedance_ctrl [all …]
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H A D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - $ref: ethernet-phy.yaml# 14 - Andrew Davis <afd@ti.com> 17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver 18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and 19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and 20 100BASE-FX Fiber protocols. 23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX [all …]
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H A D | renesas,etheravb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sergei Shtylyov <sergei.shtylyov@gmail.com> 15 - items: 16 - enum: 17 - renesas,etheravb-r8a7742 # RZ/G1H 18 - renesas,etheravb-r8a7743 # RZ/G1M 19 - renesas,etheravb-r8a7744 # RZ/G1N 20 - renesas,etheravb-r8a7745 # RZ/G1E [all …]
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H A D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 14 # The dt-schema tools will generate a select statement first by using 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 24 - $nodename [all …]
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H A D | allwinner,sun8i-a83t-emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 16 - const: allwinner,sun8i-a83t-emac 17 - const: allwinner,sun8i-h3-emac 18 - const: allwinner,sun8i-r40-gmac 19 - const: allwinner,sun8i-v3s-emac [all …]
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H A D | fsl,fec.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Guo <shawnguo@kernel.org> 11 - Wei Fang <wei.fang@nxp.com> 12 - NXP Linux Team <linux-imx@nxp.com> 15 - $ref: ethernet-controller.yaml# 20 - enum: 21 - fsl,imx25-fec 22 - fsl,imx27-fec [all …]
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H A D | mediatek-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Biao Huang <biao.huang@mediatek.com> 21 - mediatek,mt2712-gmac 22 - mediatek,mt8188-gmac 23 - mediatek,mt8195-gmac 25 - compatible 28 - $ref: snps,dwmac.yaml# [all …]
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/openbmc/u-boot/doc/device-tree-bindings/net/ |
H A D | ti,dp83867.txt | 1 * Texas Instruments - dp83867 Giga bit ethernet phy 4 - reg - The ID number for the phy, usually a small integer 5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h 7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h 9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h 11 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to 13 - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the 14 TX/RX lanes. 15 - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h 23 ethernet-phy@0 { [all …]
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/openbmc/linux/drivers/net/phy/ |
H A D | dp83867.c | 1 // SPDX-License-Identifier: GPL-2.0 13 #include <linux/delay.h> 17 #include <linux/nvmem-consumer.h> 19 #include <dt-bindings/net/ti-dp83867.h> 194 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol() 201 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol() 206 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol() 207 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol() 210 return -EINVAL; in dp83867_set_wol() 224 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol() [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | dra72-evm-revc.dts | 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 8 #include "dra72-evm-common.dtsi" 9 #include "dra72x-mmc-iodelay.dtsi" 10 #include <dt-bindings/net/ti-dp83867.h> 20 evm_1v8_sw: fixedregulator-evm_1v8 { 21 compatible = "regulator-fixed"; 22 regulator-name = "evm_1v8"; 23 regulator-min-microvolt = <1800000>; 24 regulator-max-microvolt = <1800000>; 25 vin-supply = <&smps4_reg>; [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dra72-evm-revc.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ 5 #include "dra72-evm-common.dtsi" 6 #include "dra72x-mmc-iodelay.dtsi" 7 #include <dt-bindings/net/ti-dp83867.h> 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 23 compatible = "shared-dma-pool"; 30 compatible = "shared-dma-pool"; [all …]
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
H A D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <linux/clk-provider.h> 35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one 36 * cycle of the 125MHz RGMII TX clock): 51 * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0] 57 * the automatically delay and skew automatically (internally). 60 /* An internal counter based on the "timing-adjustment" clock. The counter is 62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0]. 66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1, 67 * ...) can be configured to be 1 to compensate for a delay of about 1ns. [all …]
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H A D | dwmac-sun8i.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 11 #include <linux/mdio-mux.h> 28 /* General notes on dwmac-sun8i: 33 /* struct emac_variant - Describe dwmac-sun8i hardware variant 39 * @soc_has_internal_phy: Does the MAC embed an internal PHY 44 * @rx_delay_max: Maximum raw value for RX delay chain 45 * @tx_delay_max: Maximum raw value for TX delay chain 47 * the RX and TX delay chain registers. A 61 /* struct sunxi_priv_data - hold all sunxi private data [all …]
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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
H A D | fsl,cpm1-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: PowerQUICC CPM Time-slot assigner (TSA) controller 10 - Herve Codina <herve.codina@bootlin.com> 13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. 14 Its purpose is to route some TDM time-slots to other internal serial 20 - enum: 21 - fsl,mpc885-tsa [all …]
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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
H A D | ucc.txt | 4 - device_type : should be "network", "hldc", "uart", "transparent" 6 - compatible : could be "ucc_geth" or "fsl_atm" and so on. 7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM. 8 - reg : Offset and length of the register set for the device 9 - interrupts : <a b> where a is the interrupt number and b is a 14 - pio-handle : The phandle for the Parallel I/O port configuration. 15 - port-number : for UART drivers, the port number to use, between 0 and 3. 18 CPM UART driver, the port-number is required for the QE UART driver. 19 - soft-uart : for UART drivers, if specified this means the QE UART device 20 driver should use "Soft-UART" mode, which is needed on some SOCs that have [all …]
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/openbmc/linux/arch/arm64/boot/dts/renesas/ |
H A D | r8a779a0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC 8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/power/r8a779a0-sysc.h> 14 #address-cells = <2>; 15 #size-cells = <2>; 17 /* External CAN clock - to be overridden by boards that provide it */ 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; [all …]
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