| /openbmc/qemu/pc-bios/ |
| H A D | petalogix-s3adsp1800.dts | 193 xlnx,twc-ps-mem-0 = <0x11170>;
194 xlnx,twc-ps-mem-1 = <0x3a98>;
195 xlnx,twc-ps-mem-2 = <0x3a98>;
196 xlnx,twc-ps-mem-3 = <0x3a98>;
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| H A D | petalogix-ml605.dts | 306 xlnx,twc-ps-mem-0 = < 0x32c8 >;
307 xlnx,twc-ps-mem-1 = < 0x3a98 >;
308 xlnx,twc-ps-mem-2 = < 0x3a98 >;
309 xlnx,twc-ps-mem-3 = < 0x3a98 >;
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| /openbmc/linux/arch/microblaze/boot/dts/ |
| H A D | system.dts | 186 xlnx,twc-ps-mem-0 = <0x2af8>;
187 xlnx,twc-ps-mem-1 = <0x3a98>;
188 xlnx,twc-ps-mem-2 = <0x3a98>;
189 xlnx,twc-ps-mem-3 = <0x3a98>;
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | pinmux.c | 294 PIN(DAP2, DAP2, TWC, RSVD3, GMI),
322 PIN(SDC, PWM, TWC, SDIO3, SPI3),
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | nvidia,tegra20-car.txt | 44 16 twc
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nvidia,tegra20-pinmux.yaml | 67 spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | head_8xx.S | 270 /* Insert Guarded and Accessed flags into the TWC from the Linux PTE.
271 * It is bit 27 of both the Linux PTE and the TWC (at least
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | tegra20-paz00.dts | 182 nvidia,function = "twc";
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| /openbmc/linux/drivers/misc/eeprom/ |
| H A D | eeprom_93xx46.c | 257 /* have to wait program cycle time Twc ms */ in eeprom_93xx46_write_word()
|
| /openbmc/linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra20.c | 1950 FUNCTION(twc),
2056 MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12),
2129 MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
|
| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra20.c | 477 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
763 …TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20…
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| /openbmc/linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra20-paz00.dts | 166 nvidia,function = "twc";
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| /openbmc/linux/drivers/mtd/nand/raw/atmel/ |
| H A D | nand-controller.c | 1313 * The write cycle timing is directly matching tWC, but is also in atmel_smc_nand_prepare_smcconf()
1317 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD) in atmel_smc_nand_prepare_smcconf()
1381 * The write cycle timing is directly matching tWC, but is also in atmel_smc_nand_prepare_smcconf()
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | stm32_fmc2_nand.c | 1447 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) in stm32_fmc2_nfc_calc_timings()
1496 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) in stm32_fmc2_nfc_calc_timings()
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| H A D | denali.c | 859 * tRP, tWP, tRHOH, tRC, tWC -> RDWR_EN_LO_CNT in denali_setup_interface()
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| H A D | sunxi_nand.c | 1459 /* T15 <=> tWC */ in sunxi_nfc_setup_interface()
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| /openbmc/qemu/target/ppc/ |
| H A D | mmu_helper.c | 1323 /* XXX only check when MMUCFG[TWC] || TLBnCFG[HES] */ in helper_booke206_tlbilx3()
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | sunxi_nand.c | 1285 /* T15 <=> tWC */ in sunxi_nand_chip_set_timings()
|