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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
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/openbmc/linux/drivers/memory/tegra/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
10 tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
11 tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 This driver supports the Memory Controller (MC) hardware found on
39 tristate "NVIDIA Tegra124 External Memory Controller driver"
46 Tegra124 chips. The EMC controls the external DRAM on the board.
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
27 #include <soc/tegra/mc.h>
29 #include "mc.h"
484 struct tegra_mc *mc; member
512 /* protect shared rate-change code path */
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
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H A Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
22 #include "mc.h"
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
41 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
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H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
38 #include "mc.h"
357 struct tegra_mc *mc; member
392 /* protect shared rate-change code path */
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
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H A Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra124-mc.h>
12 #include "mc.h"
833 /* read-only */
850 /* read-only */
1158 * ISO clients need to reserve extra bandwidth up-front because in tegra124_mc_icc_aggreate()
1175 struct tegra_mc *mc = icc_provider_to_tegra_mc(data); in tegra124_mc_of_icc_xlate_extended() local
1177 unsigned int i, idx = spec->args[0]; in tegra124_mc_of_icc_xlate_extended()
1181 list_for_each_entry(node, &mc->provider.nodes, node_list) { in tegra124_mc_of_icc_xlate_extended()
1182 if (node->id != idx) in tegra124_mc_of_icc_xlate_extended()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
16 two memory channels. The Tegra124 Memory Controller handles memory requests
22 const: nvidia,tegra124-mc
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H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
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/openbmc/u-boot/arch/arm/dts/
H A Dtegra124.dtsi1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
13 compatible = "nvidia,tegra124";
14 interrupt-parent = <&lic>;
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H A Dtegra210.dtsi1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 pcie-controller@01003000 {
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/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
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H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
19 - enum:
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
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/openbmc/linux/Documentation/devicetree/bindings/devfreq/
H A Dnvidia,tegra30-actmon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
23 - nvidia,tegra30-actmon
24 - nvidia,tegra114-actmon
25 - nvidia,tegra124-actmon
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/openbmc/u-boot/arch/arm/mach-tegra/
H A Dap.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
13 #include <asm/arch/mc.h>
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/clock.h>
16 #include <asm/arch-tegra/fuse.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/scu.h>
19 #include <asm/arch-tegra/tegra.h>
20 #include <asm/arch-tegra/warmboot.h>
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H A Dboard.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
14 #include <asm/arch/mc.h>
16 #include <asm/arch-tegra/ap.h>
17 #include <asm/arch-tegra/board.h>
18 #include <asm/arch-tegra/pmc.h>
19 #include <asm/arch-tegra/sys_proto.h>
20 #include <asm/arch-tegra/warmboot.h>
53 #error tegra_cpu_is_non_secure has only been validated on Tegra124
58 * This register reads 0xffffffff in non-secure mode. This register in tegra_cpu_is_non_secure()
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra132-vde
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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/openbmc/linux/drivers/gpu/host1x/
H A Ddev.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
10 #include <linux/dma-mapping.h>
27 #include <asm/dma-iommu.h>
47 writel(v, host1x->common_regs + r); in host1x_common_writel()
52 writel(v, host1x->hv_regs + r); in host1x_hypervisor_writel()
57 return readl(host1x->hv_regs + r); in host1x_hypervisor_readl()
62 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_writel()
69 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_readl()
76 writel(v, ch->regs + r); in host1x_ch_writel()
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/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/tegra124-car.h>
15 #include <dt-bindings/reset/tegra124-car.h>
18 #include "clk-id.h"
22 * banks present in the Tegra124/132 CAR IP block. The banks are
95 #define MASK(x) (BIT(x) - 1)
995 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()
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/openbmc/linux/drivers/media/platform/nvidia/tegra-vde/
H A Dvde.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com>
10 #include <linux/dma-buf.h>
60 struct device *dev = vde->dev; in tegra_vde_alloc_bo()
66 return -ENOMEM; in tegra_vde_alloc_bo()
68 bo->vde = vde; in tegra_vde_alloc_bo()
69 bo->size = size; in tegra_vde_alloc_bo()
70 bo->dma_dir = dma_dir; in tegra_vde_alloc_bo()
71 bo->dma_attrs = DMA_ATTR_WRITE_COMBINE | in tegra_vde_alloc_bo()
74 if (!vde->domain) in tegra_vde_alloc_bo()
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/openbmc/linux/drivers/thermal/tegra/
H A Dsoctherm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
232 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
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/openbmc/openbmc/poky/meta/recipes-kernel/linux-firmware/
H A Dlinux-firmware_20250109.bb9 Firmware-Abilis \
10 & Firmware-adsp_sst \
11 & Firmware-agere \
12 & Firmware-amdgpu \
13 & Firmware-amd-ucode \
14 & Firmware-amlogic_vdec \
15 & Firmware-amphion_vpu \
16 & Firmware-atheros_firmware \
17 & Firmware-atmel \
18 & Firmware-broadcom_bcm43xx \
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/openbmc/linux/drivers/mmc/host/
H A Dsdhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
20 #include <linux/mmc/slot-gpio.h>
32 #include "sdhci-cqhci.h"
33 #include "sdhci-pltfm.h"
192 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
194 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
200 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
213 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
216 writel((val << 16) | pltfm_host->xfer_mode_shadow, in tegra_sdhci_writew()
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