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/openbmc/linux/drivers/memory/
H A Djedec_ddr_data.c49 .tZQCL = 360000,
70 .tZQCL = 360000,
91 .tZQCL = 360000,
112 .tZQCL = 360000,
H A Dof_memory.c82 ret |= of_property_read_u32(np, "tZQCL", &tim->tZQCL); in of_do_get_timings()
H A Djedec_ddr.h163 u32 tZQCL; member
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi40 tZQCL = <360000>;
62 tZQCL = <360000>;
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Demif.c39 .tZQCL = 360,
63 .tZQCL = 360,
H A Dsdram_elpida.c206 .tZQCL = 360,
229 .tZQCL = 360,
252 .tZQCL = 360,
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml92 tZQCL:
132 tZQCL = <360000>;
H A Djedec,lpddr2.yaml179 tZQCL = <360000>;
200 tZQCL = <360000>;
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3036.h71 u32 tzqcl; member
268 u32 tzqcl; member
H A Dsdram.h74 u32 tzqcl; member
H A Dddr_rk3368.h75 u32 tzqcl; member
H A Dsdram_rk322x.h107 u32 tzqcl; member
233 u32 tzqcl; member
H A Dddr_rk3288.h70 u32 tzqcl; member
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Demif.c40 .tZQCL = 360,
H A Dsdram.c628 .tZQCL = 360,
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt84 tzqcl
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun6i.h98 u32 tzqcl; /* 0x138 */ member
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun6i.c233 writel(MCTL_TZQCL, &mctl_ctl->tzqcl); in mctl_channel_init()
/openbmc/u-boot/arch/arm/include/asm/
H A Demif.h1155 u32 tZQCL; member
/openbmc/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c516 pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */ in pctl_calc_timings()