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/openbmc/linux/Documentation/devicetree/bindings/hsi/
H A Dclient-devices.txt15 - hsi-flow: RX flow type ("synchronized" or "pipeline")
38 hsi-flow = "synchronized";
H A Dnokia-modem.txt43 hsi-flow = "synchronized";
/openbmc/linux/sound/firewire/fireface/
H A Dff-protocol-latter.c32 // 0x00000040: Synchronized to word clock on BNC interface
33 // 0x00000020: Synchronized to ADAT or S/PDIF on optical interface
34 // 0x00000010: Synchronized to S/PDIF on coaxial interface
52 // 0x00000080: Synchronized to ADAT-B on 2nd optical interface
53 // 0x00000040: Synchronized to ADAT-A on 1st optical interface
54 // 0x00000020: Synchronized to AES/EBU on XLR or 2nd optical interface
55 // 0x00000010: Synchronized to word clock on BNC interface
/openbmc/linux/drivers/comedi/drivers/
H A Dadv_pci1720.c27 * The analog outputs can operate in two modes, immediate and synchronized.
28 * This driver currently does not support the synchronized output mode.
149 /* disable synchronized output, channels update when written */ in pci1720_auto_attach()
/openbmc/linux/include/uapi/linux/
H A Ddma-buf.h146 * synchronized APIs such as Vulkan to inter-op with dma-buf consumers
158 * implicitly synchronized writes to this dma-buf will wait on this
162 * write fence. All subsequent implicitly synchronized access to
H A Dtimex.h198 #define TIME_OK 0 /* clock synchronized, no leap second */
203 #define TIME_ERROR 5 /* clock not synchronized */
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,rz-mtu3.yaml43 complementary PWM and reset-synchronized PWM operation.
52 reset-synchronized PWM output is settable and allows the selection
70 to be started with any desired timing and to be synchronized with
87 The module supports PWM mode{1,2}, Reset-synchronized PWM mode and
/openbmc/qemu/migration/
H A Dmigration-stats.h42 * since we synchronized bitmaps.
50 * Number of times we have synchronized guest bitmaps.
/openbmc/linux/arch/arm/mach-omap2/
H A Ddma.c101 * a. Channel i, hardware synchronized, is enabled in configure_dma_errata()
102 * b. Another channel (Channel x), software synchronized, is enabled. in configure_dma_errata()
106 * f. A third channel (Channel y), software synchronized, is enabled. in configure_dma_errata()
/openbmc/linux/include/linux/
H A Dpvclock_gtod.h9 * and is used to keep guest time synchronized with host time.
/openbmc/linux/sound/soc/sh/rcar/
H A Dssiu.c181 * set synchronized bit here in rsnd_ssiu_init()
184 /* SSI4 is synchronized with SSI3 */ in rsnd_ssiu_init()
187 /* SSI012 are synchronized */ in rsnd_ssiu_init()
190 /* SSI0129 are synchronized */ in rsnd_ssiu_init()
/openbmc/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst347 determine offset information in SMP systems where TSCs are not synchronized.
370 practice, getting a perfectly synchronized TSC will not be possible unless all
378 may not have a TSC value that is synchronized with the rest of the system.
382 TSC is synchronized back to a state where TSC synchronization flaws, however
401 It is recommended not to trust the TSCs to remain synchronized on NUMA or
493 synchronized with real time.
551 the TSC as seen from other CPUs, even in an otherwise perfectly synchronized
H A Dmmu.rst241 are synchronized when the guest executes invlpg or flushes its tlb by
257 emulations if the page needs to be write-protected (see "Synchronized
271 Synchronized and unsynchronized pages
305 - synchronized shadow pages are write protected (*)
/openbmc/qemu/include/semihosting/
H A Dconsole.h24 * - CPUState is synchronized before calling this function
/openbmc/linux/arch/ia64/kernel/
H A Dtime.c324 /* On IA64 in an SMP configuration ITCs are never accurately synchronized. in ia64_init_itm()
339 * ITC is drifty and we have not synchronized the ITCs in smpboot.c. in ia64_init_itm()
406 * migrates to another CPU, that the ITC values are synchronized across
/openbmc/openbmc/poky/meta/recipes-core/systemd/systemd-serialgetty/
H A Dserial-getty@.service20 # sure that this is synchronized before getty.target, even though
/openbmc/openbmc/meta-ibm/recipes-support/chrony/chrony/huygens/
H A Dchrony.conf32 # Serve time even if not synchronized to any NTP server.
/openbmc/linux/net/core/
H A Ddev_addr_lists.c415 * __hw_addr_ref_unsync_dev - Remove synchronized addresses and references on
417 * @list: address list to remove synchronized addresses (references on it) from
451 * __hw_addr_unsync_dev - Remove synchronized addresses from device
452 * @list: address list to remove synchronized addresses from
780 * dev_uc_unsync - Remove synchronized addresses from the destination device
1003 * dev_mc_unsync - Remove synchronized addresses from the destination device
/openbmc/linux/arch/x86/include/asm/
H A Dtsc.h51 * Boot-time check whether the TSCs are synchronized across
/openbmc/linux/tools/testing/selftests/drivers/net/ocelot/
H A Dpsfp.sh182 # Set up swp1 as a master PHC for h1, synchronized to the local
187 # synchronizing h1 to swp1 via PTP, h2 is also implicitly synchronized
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/chrony/chrony/
H A Dchrony.conf41 # Serve time even if not synchronized to any NTP server.
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6-orangepi-lite2.dts43 * Before the kernel can support synchronized
/openbmc/linux/Documentation/driver-api/
H A Dpps.rst77 synchronized with PPS through USB. With USB 2.0, jitter may decrease
203 computers' clock to be synchronized very tightly. One way to do this is to
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.h46 /* pipe to which cd2x update is synchronized */
/openbmc/u-boot/common/
H A Dmemsize.c14 * memory must be synchronized.

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