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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dbrcm,bcm63xx-hsspi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
19 brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to
20 use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
37 - const: brcm,bcm6328-hsspi
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm6855.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
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H A Dbcm6756.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
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/openbmc/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm6813.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
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H A Dbcm4912.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
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/openbmc/linux/drivers/spi/
H A Dspi-bcmbca-hsspi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2000-2010 Broadcom Corporation
6 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright 2019-2022 Broadcom Ltd
17 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
129 struct spi_controller *ctrl = dev_get_drvdata(dev); in wait_mode_show() local
130 struct bcmbca_hsspi *bs = spi_controller_get_devdata(ctrl); in wait_mode_show()
132 return sprintf(buf, "%d\n", bs->wait_mode); in wait_mode_show()
138 struct spi_controller *ctrl = dev_get_drvdata(dev); in wait_mode_store() local
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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
47 /* Local-Access Registers & ECM Registers */
123 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
298 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
300 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
365 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
419 u32 tr64; /* TX & RX 64-byte Frame Counter */
420 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
421 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
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