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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SMI (Smart Multimedia Interface) Common
11 - Yong Wu <yong.wu@mediatek.com>
16 MediaTek SMI have two generations of HW architecture, here is the list
21 There's slight differences between the two SMI, for generation 2, the
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
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/openbmc/linux/drivers/memory/
H A Dmtk-smi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
19 #include <soc/mediatek/smi.h>
20 #include <dt-bindings/memory/mt2701-larb-port.h>
21 #include <dt-bindings/memory/mtk-memory-port.h>
23 /* SMI COMMON */
39 /* SMI LARB */
66 * or non-security.
104 MTK_SMI_GEN2, /* gen2 smi common */
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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
33 SMI Common(Smart Multimedia Interface Common)
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/openbmc/openbmc-test-automation/lib/snmp/
H A Dredfish_snmp_utils.robot17 ... xyz.openbmc_project.Logging.Create Create ssa{ss} xyz.openbmc_project.Common.Error.InternalFai…
21 ... xyz.openbmc_project.Logging.Create Create ssa{ss} xyz.openbmc_project.Common.Error.Timeout
26 ... xyz.openbmc_project.Logging.Create Create ssa{ss} xyz.openbmc_project.Common.Error.TestError2
29 ${SNMP_TRAP_BMC_INTERNAL_FAILURE} xyz.openbmc_project.Common.Error.InternalFailure
30 ${SNMP_TRAP_BMC_CALLOUT_ERROR} xyz.openbmc_project.Common.Error.Timeout
32 ${SNMP_TRAP_BMC_INFORMATIONAL_ERROR} xyz.openbmc_project.Common.Error.TestError2
218 # 2021-06-16 07:05:29 xx.xx.xx.xx [UDP: [xx.xx.xx.xx]:58154->[xx.xx.xx.xx]:xxx]:
219 # DISMAN-EVENT-MIB::sysUpTimeInstance = Timeticks: (2100473) 5:50:04.73
220 # SNMPv2-MIB::snmpTrapOID.0 = OID: SNMPv2-SMI::enterprises.49871.1.0.0.1
221 …# SNMPv2-SMI::enterprises.49871.1.0.1.1 = Gauge32: 369 SNMPv2-SMI::enterprises.49871.1.0.1.2 =…
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/openbmc/openbmc-test-automation/redfish/events/
H A Dtest_bmc_snmp_config.robot4 ... configuration refer http://www.net-snmp.org/.
21 ... xyz.openbmc_project.Logging.Create Create ssa{ss} xyz.openbmc_project.Common.Error.InternalFai…
25 ... xyz.openbmc_project.Logging.Create Create ssa{ss} xyz.openbmc_project.Common.Error.Timeout
30 ... xyz.openbmc_project.Logging.Create Create ssa{ss} xyz.openbmc_project.Common.Error.TestError2
33 ${CMD_DEBUG_TRABALL_ERROR}= /tmp/tarball/bin/logging-test -c AutoTestSimple
34 ${SNMP_TRAP_BMC_INTERNAL_FAILURE} xyz.openbmc_project.Common.Error.InternalFailure
35 ${SNMP_TRAP_BMC_CALLOUT_ERROR} xyz.openbmc_project.Common.Error.Timeout
36 ${SNMP_TRAP_BMC_INFORMATIONAL_ERROR} xyz.openbmc_project.Common.Error.TestError2
58 [Documentation] Configure SNMP Manager On BMC with out-of range port and verify.
90 [Documentation] Configure SNMP Manager On BMC with out-of range IP and verify.
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/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/openbmc/linux/arch/arm/mach-omap2/
H A Dsleep34xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-dp@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
57 * with non-Thumb-2-capable firmware.
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
98 smc #1 @ call SMI monitor (smi #1)
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
121 * - only the minimum set of functions gets copied to internal SRAM at boot
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/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
33 compatible = "mediatek,mt8167-apmixedsys", "syscon";
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H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
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H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
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H A Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
10 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
11 #include <dt-bindings/memory/mt6795-larb-port.h>
12 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
13 #include <dt-bindings/power/mt6795-power.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
18 interrupt-parent = <&sysirq>;
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H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-98dx3236-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
45 mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
46 mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
H A Dmarvell,armada-37xx-pinctrl.txt12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
17 common pinctrl bindings used by client devices, including the meaning
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
33 - pins 20-24
34 - functions jtag, gpio
37 - pins 8-10
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H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
35 mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
38 mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
H A Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
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/openbmc/u-boot/arch/x86/lib/
H A Dacpi.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <common.h>
13 if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0) in acpi_valid_rsdp()
22 if ((rsdp->revision > 1) && in acpi_valid_rsdp()
23 (table_compute_checksum((void *)rsdp, rsdp->length) != 0)) in acpi_valid_rsdp()
49 rsdt = (struct acpi_rsdt *)(uintptr_t)rsdp->rsdt_address; in acpi_find_fadt()
51 end = (char *)rsdt + rsdt->header.length; in acpi_find_fadt()
54 for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { in acpi_find_fadt()
55 fadt = (struct acpi_fadt *)(uintptr_t)rsdt->entry[i]; in acpi_find_fadt()
75 facs = (struct acpi_facs *)(uintptr_t)fadt->firmware_ctrl; in acpi_find_wakeup_vector()
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/openbmc/u-boot/drivers/mtd/
H A Dst_smi.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <common.h>
81 * smi_wait_xfer_finish - Wait until TFF is set in status register
91 if (readl(&smicntl->smi_sr) & TFF) in smi_wait_xfer_finish()
98 return -1; in smi_wait_xfer_finish()
102 * smi_read_id - Read flash id
112 writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); in smi_read_id()
113 writel(READ_ID, &smicntl->smi_tr); in smi_read_id()
115 &smicntl->smi_cr2); in smi_read_id()
118 return -EIO; in smi_read_id()
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/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,armada-37xx-pinctrl.txt7 ------------------------
11 Refer to pinctrl-bindings.txt in this directory for details of the
12 common pinctrl bindings used by client devices, including the meaning
17 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
19 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
28 - pins 20-24
29 - functions jtag, gpio
32 - pins 8-10
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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Drealtek.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - Linus Walleij <linus.walleij@linaro.org>
17 switches. They can be controlled using different interfaces, like SMI,
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
26 The MDIO-connected switches use MDIO protocol to access their registers.
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/openbmc/linux/drivers/mmc/host/
H A Dcavium.c9 * Copyright (C) 2012-2017 Cavium Inc.
18 #include <linux/dma-direction.h>
19 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
46 * being used. However, non-MMC devices like SD use command and
128 cr = cvm_mmc_cr_types + (cmd->opcode & 0x3f); in cvm_mmc_get_cr_mods()
129 hardware_ctype = cr->ctype; in cvm_mmc_get_cr_mods()
130 hardware_rtype = cr->rtype; in cvm_mmc_get_cr_mods()
131 if (cmd->opcode == MMC_GEN_CMD) in cvm_mmc_get_cr_mods()
132 hardware_ctype = (cmd->arg & 1) ? 1 : 2; in cvm_mmc_get_cr_mods()
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/openbmc/linux/Documentation/arch/x86/
H A Dmicrocode.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
8 - Borislav Petkov <bp@suse.de>
9 - Ashok Raj <ashok.raj@intel.com>
13 updating the microcode on platforms beyond the OEM End-Of-Life support,
14 and updating the microcode on long-running systems without rebooting.
39 During BSP (BootStrapping Processor) boot (pre-SMP), the kernel
56 if [ -z "$1" ]; then
66 rm -rf $TMPDIR
70 mkdir -p $DSTDIR
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/openbmc/u-boot/drivers/net/
H A Darmada100_fec.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Ajay Bhargav <contact@8051projects.net>
12 #include <common.h>
31 struct armdfec_reg *regs = darmdfec->regs; in eth_dump_regs()
34 printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr)); in eth_dump_regs()
35 printf("offset: smi, value: 0x%x\n", readl(&regs->smi)); in eth_dump_regs()
48 while (--timeout) { in armdfec_phy_timeout()
63 struct eth_device *dev = eth_get_dev_by_name(bus->name); in smi_reg_read()
65 struct armdfec_reg *regs = darmdfec->regs; in smi_reg_read()
69 val = readl(&regs->phyadr); in smi_reg_read()
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